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Merge pull request #251 from Subv/tic_tsc
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
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commit
b2d7c92cae
@ -62,7 +62,34 @@ public:
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union {
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union {
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struct {
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struct {
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INSERT_PADDING_WORDS(0x582);
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INSERT_PADDING_WORDS(0x557);
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struct {
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u32 tsc_address_high;
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u32 tsc_address_low;
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u32 tsc_limit;
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GPUVAddr TSCAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(tsc_address_high) << 32) | tsc_address_low);
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}
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} tsc;
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INSERT_PADDING_WORDS(0x3);
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struct {
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u32 tic_address_high;
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u32 tic_address_low;
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u32 tic_limit;
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GPUVAddr TICAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(tic_address_high) << 32) | tic_address_low);
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}
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} tic;
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INSERT_PADDING_WORDS(0x22);
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struct {
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struct {
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u32 code_address_high;
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u32 code_address_high;
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u32 code_address_low;
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u32 code_address_low;
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@ -264,6 +291,8 @@ private:
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(query, 0x6C0);
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