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Pica/CommandProcessor: Add support for integer uniforms.
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@ -173,6 +173,19 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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break;
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[3], 0x2b4):
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{
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int index = (id - PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1));
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auto values = registers.vs_int_uniforms[index];
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VertexShader::GetIntUniform(index) = Math::Vec4<u8>(values.x, values.y, values.z, values.w);
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LOG_ERROR(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x",
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index, values.x.Value(), values.y.Value(), values.z.Value(), values.w.Value());
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[2], 0x2c3):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[2], 0x2c3):
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@ -495,8 +495,14 @@ struct Regs {
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INSERT_PADDING_WORDS(0x51);
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INSERT_PADDING_WORDS(0x51);
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BitField<0, 16, u32> vs_bool_uniforms;
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BitField<0, 16, u32> vs_bool_uniforms;
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union {
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BitField< 0, 8, u32> x;
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BitField< 8, 8, u32> y;
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BitField<16, 8, u32> z;
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BitField<24, 8, u32> w;
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} vs_int_uniforms[4];
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INSERT_PADDING_WORDS(0x9);
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INSERT_PADDING_WORDS(0x5);
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// Offset to shader program entry point (in words)
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> vs_main_offset;
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BitField<0, 16, u32> vs_main_offset;
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@ -625,6 +631,7 @@ struct Regs {
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(trigger_draw_indexed);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_int_uniforms);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_uniform_setup);
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ADD_FIELD(vs_uniform_setup);
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@ -696,6 +703,7 @@ ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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@ -30,6 +30,8 @@ static struct {
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Math::Vec4<float24> f[96];
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Math::Vec4<float24> f[96];
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std::array<bool,16> b;
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std::array<bool,16> b;
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std::array<Math::Vec4<u8>,4> i;
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} shader_uniforms;
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} shader_uniforms;
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// TODO: Not sure where the shader binary and swizzle patterns are supposed to be loaded to!
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// TODO: Not sure where the shader binary and swizzle patterns are supposed to be loaded to!
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@ -57,6 +59,11 @@ bool& GetBoolUniform(u32 index)
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return shader_uniforms.b[index];
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return shader_uniforms.b[index];
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}
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}
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Math::Vec4<u8>& GetIntUniform(u32 index)
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{
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return shader_uniforms.i[index];
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}
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const std::array<u32, 1024>& GetShaderBinary()
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const std::array<u32, 1024>& GetShaderBinary()
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{
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{
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return shader_memory;
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return shader_memory;
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@ -73,6 +73,7 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes);
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Math::Vec4<float24>& GetFloatUniform(u32 index);
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Math::Vec4<float24>& GetFloatUniform(u32 index);
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bool& GetBoolUniform(u32 index);
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bool& GetBoolUniform(u32 index);
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Math::Vec4<u8>& GetIntUniform(u32 index);
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const std::array<u32, 1024>& GetShaderBinary();
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const std::array<u32, 1024>& GetShaderBinary();
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const std::array<u32, 1024>& GetSwizzlePatterns();
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const std::array<u32, 1024>& GetSwizzlePatterns();
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