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shader: Account for 33-bit IADD3 scenario
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@ -36,8 +36,12 @@ enum class Half : u64 {
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switch (shift) {
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switch (shift) {
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case Shift::None:
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case Shift::None:
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return value;
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return value;
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case Shift::Right:
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case Shift::Right: {
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return ir.ShiftRightLogical(value, ir.Imm32(16));
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// 33-bit RS IADD3 edge case
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const IR::U1 edge_case{ir.GetCarryFromOp(value)};
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const IR::U32 shifted{ir.ShiftRightLogical(value, ir.Imm32(16))};
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return IR::U32{ir.Select(edge_case, ir.IAdd(shifted, ir.Imm32(0x10000)), shifted)};
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}
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case Shift::Left:
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case Shift::Left:
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return ir.ShiftLeftLogical(value, ir.Imm32(16));
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return ir.ShiftLeftLogical(value, ir.Imm32(16));
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}
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}
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@ -67,6 +71,10 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_a, IR::U32 op_b, IR::U32 o
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}
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}
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IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)};
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IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)};
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if (iadd3.x != 0) {
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if (iadd3.x != 0) {
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// TODO: How does RS behave when X is set?
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if (shift == Shift::Right) {
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throw NotImplementedException("IADD3 X+RS");
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}
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const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
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const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
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lhs_1 = v.ir.IAdd(lhs_1, carry);
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lhs_1 = v.ir.IAdd(lhs_1, carry);
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}
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}
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