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Merge pull request #3601 from ReinUsesLisp/some-shader-encodings
video_core/shader: Add some instruction and S2R encodings
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commit
b96fd0bd0e
@ -1712,6 +1712,7 @@ public:
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BRK,
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DEPBAR,
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VOTE,
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VOTE_VTG,
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SHFL,
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FSWZADD,
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BFE_C,
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@ -1758,6 +1759,7 @@ public:
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IPA,
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OUT_R, // Emit vertex/primitive
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ISBERD,
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BAR,
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MEMBAR,
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VMAD,
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VSETP,
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@ -1842,7 +1844,7 @@ public:
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MOV_C,
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MOV_R,
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MOV_IMM,
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MOV_SYS,
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S2R,
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MOV32_IMM,
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SHL_C,
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SHL_R,
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@ -2026,6 +2028,7 @@ private:
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INST("111000110000----", Id::EXIT, Type::Flow, "EXIT"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("0101000011011---", Id::VOTE, Type::Warp, "VOTE"),
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INST("0101000011100---", Id::VOTE_VTG, Type::Warp, "VOTE_VTG"),
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INST("1110111100010---", Id::SHFL, Type::Warp, "SHFL"),
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INST("0101000011111---", Id::FSWZADD, Type::Warp, "FSWZADD"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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@ -2063,6 +2066,7 @@ private:
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INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
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INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
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INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
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INST("1111000010101---", Id::BAR, Type::Trivial, "BAR"),
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INST("1110111110011---", Id::MEMBAR, Type::Trivial, "MEMBAR"),
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INST("01011111--------", Id::VMAD, Type::Video, "VMAD"),
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INST("0101000011110---", Id::VSETP, Type::Video, "VSETP"),
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@ -2134,7 +2138,7 @@ private:
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INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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INST("1111000011001---", Id::MOV_SYS, Type::Trivial, "MOV_SYS"),
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INST("1111000011001---", Id::S2R, Type::Trivial, "S2R"),
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INST("000000010000----", Id::MOV32_IMM, Type::ArithmeticImmediate, "MOV32_IMM"),
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INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
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INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
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@ -71,18 +71,24 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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bb.push_back(Operation(OperationCode::Discard));
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break;
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}
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case OpCode::Id::MOV_SYS: {
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case OpCode::Id::S2R: {
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const Node value = [this, instr] {
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switch (instr.sys20) {
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case SystemVariable::LaneId:
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LOG_WARNING(HW_GPU, "MOV_SYS instruction with LaneId is incomplete");
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LOG_WARNING(HW_GPU, "S2R instruction with LaneId is incomplete");
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return Immediate(0U);
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case SystemVariable::InvocationId:
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return Operation(OperationCode::InvocationId);
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case SystemVariable::Ydirection:
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return Operation(OperationCode::YNegate);
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case SystemVariable::InvocationInfo:
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LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
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LOG_WARNING(HW_GPU, "S2R instruction with InvocationInfo is incomplete");
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return Immediate(0U);
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case SystemVariable::WscaleFactorXY:
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UNIMPLEMENTED_MSG("S2R WscaleFactorXY is not implemented");
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return Immediate(0U);
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case SystemVariable::WscaleFactorZ:
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UNIMPLEMENTED_MSG("S2R WscaleFactorZ is not implemented");
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return Immediate(0U);
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case SystemVariable::Tid: {
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Node value = Immediate(0);
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@ -359,6 +359,9 @@ Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) const {
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switch (cc) {
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case Tegra::Shader::ConditionCode::NEU:
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return GetInternalFlag(InternalFlag::Zero, true);
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case Tegra::Shader::ConditionCode::FCSM_TR:
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UNIMPLEMENTED_MSG("EXIT.FCSM_TR is not implemented");
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return MakeNode<PredicateNode>(Pred::NeverExecute, false);
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default:
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UNIMPLEMENTED_MSG("Unimplemented condition code: {}", static_cast<u32>(cc));
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return MakeNode<PredicateNode>(Pred::NeverExecute, false);
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