mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-22 00:53:23 +02:00
shader: Implement FCMP
still need to configure some settings for NV denorm flush and intel NaN
This commit is contained in:
parent
3a63fa0477
commit
ba8c1d2eb4
@ -67,6 +67,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/find_leading_one.cpp
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frontend/maxwell/translate/impl/find_leading_one.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_compare.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_multi_function.cpp
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frontend/maxwell/translate/impl/floating_point_multi_function.cpp
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@ -232,6 +232,7 @@ Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitFPIsNan32(EmitContext& ctx, Id value);
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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void EmitIAdd64(EmitContext& ctx);
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void EmitIAdd64(EmitContext& ctx);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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@ -346,4 +346,8 @@ Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs);
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return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs);
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}
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}
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Id EmitFPIsNan32(EmitContext& ctx, Id value) {
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return ctx.OpIsNan(ctx.U1, value);
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}
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} // namespace Shader::Backend::SPIRV
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} // namespace Shader::Backend::SPIRV
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@ -697,93 +697,107 @@ F16F32F64 IREmitter::FPTrunc(const F16F32F64& value, FpControl control) {
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}
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}
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}
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}
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U1 IREmitter::FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control, bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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switch (lhs.Type()) {
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switch (lhs.Type()) {
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdEqual16 : Opcode::FPUnordEqual16, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdEqual16 : Opcode::FPUnordEqual16, Flags{control},
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lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdEqual32 : Opcode::FPUnordEqual32, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdEqual32 : Opcode::FPUnordEqual32, Flags{control},
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lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdEqual64 : Opcode::FPUnordEqual64, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdEqual64 : Opcode::FPUnordEqual64, Flags{control},
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lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control,
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bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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switch (lhs.Type()) {
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switch (lhs.Type()) {
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual16 : Opcode::FPUnordNotEqual16, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual16 : Opcode::FPUnordNotEqual16,
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Flags{control}, lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual32 : Opcode::FPUnordNotEqual32, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual32 : Opcode::FPUnordNotEqual32,
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Flags{control}, lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual64 : Opcode::FPUnordNotEqual64, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual64 : Opcode::FPUnordNotEqual64,
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Flags{control}, lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control,
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bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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switch (lhs.Type()) {
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switch (lhs.Type()) {
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan16 : Opcode::FPUnordLessThan16, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan16 : Opcode::FPUnordLessThan16,
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Flags{control}, lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan32 : Opcode::FPUnordLessThan32, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan32 : Opcode::FPUnordLessThan32,
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Flags{control}, lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan64 : Opcode::FPUnordLessThan64, lhs, rhs);
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan64 : Opcode::FPUnordLessThan64,
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Flags{control}, lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control,
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bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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switch (lhs.Type()) {
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switch (lhs.Type()) {
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan16 : Opcode::FPUnordGreaterThan16, lhs,
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan16 : Opcode::FPUnordGreaterThan16,
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rhs);
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Flags{control}, lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan32 : Opcode::FPUnordGreaterThan32, lhs,
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan32 : Opcode::FPUnordGreaterThan32,
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rhs);
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Flags{control}, lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan64 : Opcode::FPUnordGreaterThan64, lhs,
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan64 : Opcode::FPUnordGreaterThan64,
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rhs);
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Flags{control}, lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPLessThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPLessThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control,
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bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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switch (lhs.Type()) {
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switch (lhs.Type()) {
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual16 : Opcode::FPUnordLessThanEqual16,
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual16 : Opcode::FPUnordLessThanEqual16,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual32 : Opcode::FPUnordLessThanEqual32,
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual32 : Opcode::FPUnordLessThanEqual32,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual64 : Opcode::FPUnordLessThanEqual64,
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual64 : Opcode::FPUnordLessThanEqual64,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered) {
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U1 IREmitter::FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control,
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bool ordered) {
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if (lhs.Type() != rhs.Type()) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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}
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@ -791,20 +805,32 @@ U1 IREmitter::FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs, boo
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case Type::F16:
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case Type::F16:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual16
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual16
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: Opcode::FPUnordGreaterThanEqual16,
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: Opcode::FPUnordGreaterThanEqual16,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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case Type::F32:
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case Type::F32:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual32
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual32
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: Opcode::FPUnordGreaterThanEqual32,
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: Opcode::FPUnordGreaterThanEqual32,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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case Type::F64:
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual64
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThanEqual64
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: Opcode::FPUnordGreaterThanEqual64,
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: Opcode::FPUnordGreaterThanEqual64,
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lhs, rhs);
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Flags{control}, lhs, rhs);
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default:
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default:
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ThrowInvalidType(lhs.Type());
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ThrowInvalidType(lhs.Type());
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}
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}
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}
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}
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U1 IREmitter::FPIsNan(const F32& value) {
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return Inst<U1>(Opcode::FPIsNan32, value);
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}
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U1 IREmitter::FPOrdered(const F32& lhs, const F32& rhs) {
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return LogicalAnd(LogicalNot(FPIsNan(lhs)), LogicalNot(FPIsNan(rhs)));
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}
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U1 IREmitter::FPUnordered(const F32& lhs, const F32& rhs) {
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return LogicalOr(FPIsNan(lhs), FPIsNan(rhs));
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}
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U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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if (a.Type() != b.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", a.Type(), b.Type());
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throw InvalidArgument("Mismatching types {} and {}", a.Type(), b.Type());
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@ -140,14 +140,21 @@ public:
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[[nodiscard]] F16F32F64 FPCeil(const F16F32F64& value, FpControl control = {});
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[[nodiscard]] F16F32F64 FPCeil(const F16F32F64& value, FpControl control = {});
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[[nodiscard]] F16F32F64 FPTrunc(const F16F32F64& value, FpControl control = {});
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[[nodiscard]] F16F32F64 FPTrunc(const F16F32F64& value, FpControl control = {});
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[[nodiscard]] U1 FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
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[[nodiscard]] U1 FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
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[[nodiscard]] U1 FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
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bool ordered = true);
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[[nodiscard]] U1 FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
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[[nodiscard]] U1 FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
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[[nodiscard]] U1 FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
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bool ordered = true);
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[[nodiscard]] U1 FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
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bool ordered = true);
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[[nodiscard]] U1 FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs,
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FpControl control = {}, bool ordered = true);
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[[nodiscard]] U1 FPLessThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
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[[nodiscard]] U1 FPLessThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
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bool ordered = true);
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FpControl control = {}, bool ordered = true);
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[[nodiscard]] U1 FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
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[[nodiscard]] U1 FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
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bool ordered = true);
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FpControl control = {}, bool ordered = true);
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[[nodiscard]] U1 FPIsNan(const F32& value);
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[[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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@ -197,6 +197,7 @@ OPCODE(FPTrunc16, F16, F16,
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OPCODE(FPTrunc32, F32, F32, )
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OPCODE(FPTrunc32, F32, F32, )
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OPCODE(FPTrunc64, F64, F64, )
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OPCODE(FPTrunc64, F64, F64, )
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<<<<<<< HEAD
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OPCODE(FPOrdEqual16, U1, F16, F16, )
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OPCODE(FPOrdEqual16, U1, F16, F16, )
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OPCODE(FPOrdEqual32, U1, F32, F32, )
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OPCODE(FPOrdEqual32, U1, F32, F32, )
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OPCODE(FPOrdEqual64, U1, F64, F64, )
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OPCODE(FPOrdEqual64, U1, F64, F64, )
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@ -233,6 +234,7 @@ OPCODE(FPOrdGreaterThanEqual64, U1, F64,
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OPCODE(FPUnordGreaterThanEqual16, U1, F16, F16, )
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OPCODE(FPUnordGreaterThanEqual16, U1, F16, F16, )
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OPCODE(FPUnordGreaterThanEqual32, U1, F32, F32, )
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OPCODE(FPUnordGreaterThanEqual32, U1, F32, F32, )
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OPCODE(FPUnordGreaterThanEqual64, U1, F64, F64, )
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OPCODE(FPUnordGreaterThanEqual64, U1, F64, F64, )
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OPCODE(FPIsNan32, U1, F32, )
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// Integer operations
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// Integer operations
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OPCODE(IAdd32, U32, U32, U32, )
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OPCODE(IAdd32, U32, U32, U32, )
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@ -0,0 +1,116 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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||||||
|
enum class FPCompareOp : u64 {
|
||||||
|
F,
|
||||||
|
LT,
|
||||||
|
EQ,
|
||||||
|
LE,
|
||||||
|
GT,
|
||||||
|
NE,
|
||||||
|
GE,
|
||||||
|
NUM,
|
||||||
|
Nan,
|
||||||
|
LTU,
|
||||||
|
EQU,
|
||||||
|
LEU,
|
||||||
|
GTU,
|
||||||
|
NEU,
|
||||||
|
GEU,
|
||||||
|
T,
|
||||||
|
};
|
||||||
|
|
||||||
|
bool IsCompareOpOrdered(FPCompareOp op) {
|
||||||
|
switch (op) {
|
||||||
|
case FPCompareOp::LTU:
|
||||||
|
case FPCompareOp::EQU:
|
||||||
|
case FPCompareOp::LEU:
|
||||||
|
case FPCompareOp::GTU:
|
||||||
|
case FPCompareOp::NEU:
|
||||||
|
case FPCompareOp::GEU:
|
||||||
|
return false;
|
||||||
|
default:
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
IR::U1 FloatingPointCompare(IR::IREmitter& ir, const IR::F32& operand_1, const IR::F32& operand_2,
|
||||||
|
FPCompareOp compare_op, IR::FpControl control) {
|
||||||
|
const bool ordered{IsCompareOpOrdered(compare_op)};
|
||||||
|
switch (compare_op) {
|
||||||
|
case FPCompareOp::F:
|
||||||
|
return ir.Imm1(false);
|
||||||
|
case FPCompareOp::LT:
|
||||||
|
case FPCompareOp::LTU:
|
||||||
|
return ir.FPLessThan(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::EQ:
|
||||||
|
case FPCompareOp::EQU:
|
||||||
|
return ir.FPEqual(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::LE:
|
||||||
|
case FPCompareOp::LEU:
|
||||||
|
return ir.FPLessThanEqual(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::GT:
|
||||||
|
case FPCompareOp::GTU:
|
||||||
|
return ir.FPGreaterThan(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::NE:
|
||||||
|
case FPCompareOp::NEU:
|
||||||
|
return ir.FPNotEqual(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::GE:
|
||||||
|
case FPCompareOp::GEU:
|
||||||
|
return ir.FPGreaterThanEqual(operand_1, operand_2, control, ordered);
|
||||||
|
case FPCompareOp::NUM:
|
||||||
|
return ir.FPOrdered(operand_1, operand_2);
|
||||||
|
case FPCompareOp::Nan:
|
||||||
|
return ir.FPUnordered(operand_1, operand_2);
|
||||||
|
case FPCompareOp::T:
|
||||||
|
return ir.Imm1(true);
|
||||||
|
default:
|
||||||
|
throw NotImplementedException("Invalid compare op {}", compare_op);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void FCMP(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::F32& operand) {
|
||||||
|
union {
|
||||||
|
u64 insn;
|
||||||
|
BitField<0, 8, IR::Reg> dest_reg;
|
||||||
|
BitField<8, 8, IR::Reg> src_reg;
|
||||||
|
BitField<47, 1, u64> ftz;
|
||||||
|
BitField<48, 4, FPCompareOp> compare_op;
|
||||||
|
} const fcmp{insn};
|
||||||
|
|
||||||
|
const IR::F32 zero{v.ir.Imm32(0.0f)};
|
||||||
|
const IR::F32 neg_zero{v.ir.Imm32(-0.0f)};
|
||||||
|
IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
|
||||||
|
const IR::U1 cmp_result{FloatingPointCompare(v.ir, operand, zero, fcmp.compare_op, control)};
|
||||||
|
const IR::U32 src_reg{v.X(fcmp.src_reg)};
|
||||||
|
const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};
|
||||||
|
|
||||||
|
v.X(fcmp.dest_reg, result);
|
||||||
|
}
|
||||||
|
} // Anonymous namespace
|
||||||
|
|
||||||
|
void TranslatorVisitor::FCMP_reg(u64 insn) {
|
||||||
|
FCMP(*this, insn, GetReg20(insn), GetFloatReg39(insn));
|
||||||
|
}
|
||||||
|
|
||||||
|
void TranslatorVisitor::FCMP_rc(u64 insn) {
|
||||||
|
FCMP(*this, insn, GetReg39(insn), GetFloatCbuf(insn));
|
||||||
|
}
|
||||||
|
|
||||||
|
void TranslatorVisitor::FCMP_cr(u64 insn) {
|
||||||
|
FCMP(*this, insn, GetCbuf(insn), GetFloatReg39(insn));
|
||||||
|
}
|
||||||
|
|
||||||
|
void TranslatorVisitor::FCMP_imm(u64 insn) {
|
||||||
|
FCMP(*this, insn, GetReg39(insn), GetFloatImm20(insn));
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace Shader::Maxwell
|
@ -201,22 +201,6 @@ void TranslatorVisitor::FCHK_imm(u64) {
|
|||||||
ThrowNotImplemented(Opcode::FCHK_imm);
|
ThrowNotImplemented(Opcode::FCHK_imm);
|
||||||
}
|
}
|
||||||
|
|
||||||
void TranslatorVisitor::FCMP_reg(u64) {
|
|
||||||
ThrowNotImplemented(Opcode::FCMP_reg);
|
|
||||||
}
|
|
||||||
|
|
||||||
void TranslatorVisitor::FCMP_rc(u64) {
|
|
||||||
ThrowNotImplemented(Opcode::FCMP_rc);
|
|
||||||
}
|
|
||||||
|
|
||||||
void TranslatorVisitor::FCMP_cr(u64) {
|
|
||||||
ThrowNotImplemented(Opcode::FCMP_cr);
|
|
||||||
}
|
|
||||||
|
|
||||||
void TranslatorVisitor::FCMP_imm(u64) {
|
|
||||||
ThrowNotImplemented(Opcode::FCMP_imm);
|
|
||||||
}
|
|
||||||
|
|
||||||
void TranslatorVisitor::FMNMX_reg(u64) {
|
void TranslatorVisitor::FMNMX_reg(u64) {
|
||||||
ThrowNotImplemented(Opcode::FMNMX_reg);
|
ThrowNotImplemented(Opcode::FMNMX_reg);
|
||||||
}
|
}
|
||||||
|
@ -256,7 +256,19 @@ void VisitFpModifiers(Info& info, IR::Inst& inst) {
|
|||||||
case IR::Opcode::FPRoundEven32:
|
case IR::Opcode::FPRoundEven32:
|
||||||
case IR::Opcode::FPFloor32:
|
case IR::Opcode::FPFloor32:
|
||||||
case IR::Opcode::FPCeil32:
|
case IR::Opcode::FPCeil32:
|
||||||
case IR::Opcode::FPTrunc32: {
|
case IR::Opcode::FPTrunc32:
|
||||||
|
case IR::Opcode::FPOrdEqual32:
|
||||||
|
case IR::Opcode::FPUnordEqual32:
|
||||||
|
case IR::Opcode::FPOrdNotEqual32:
|
||||||
|
case IR::Opcode::FPUnordNotEqual32:
|
||||||
|
case IR::Opcode::FPOrdLessThan32:
|
||||||
|
case IR::Opcode::FPUnordLessThan32:
|
||||||
|
case IR::Opcode::FPOrdGreaterThan32:
|
||||||
|
case IR::Opcode::FPUnordGreaterThan32:
|
||||||
|
case IR::Opcode::FPOrdLessThanEqual32:
|
||||||
|
case IR::Opcode::FPUnordLessThanEqual32:
|
||||||
|
case IR::Opcode::FPOrdGreaterThanEqual32:
|
||||||
|
case IR::Opcode::FPUnordGreaterThanEqual32: {
|
||||||
const auto control{inst.Flags<IR::FpControl>()};
|
const auto control{inst.Flags<IR::FpControl>()};
|
||||||
switch (control.fmz_mode) {
|
switch (control.fmz_mode) {
|
||||||
case IR::FmzMode::DontCare:
|
case IR::FmzMode::DontCare:
|
||||||
|
Loading…
Reference in New Issue
Block a user