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gl_shader_decompiler: Implement IADD instruction.
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@ -264,7 +264,7 @@ union Instruction {
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BitField<39, 5, u64> shift_amount;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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} iscadd;
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} alu_integer;
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union {
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BitField<20, 8, u64> shift_position;
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@ -434,6 +434,9 @@ public:
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FMUL_R,
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FMUL_IMM,
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FMUL32_IMM,
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IADD_C,
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IADD_R,
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IADD_IMM,
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ISCADD_C, // Scale and Add
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ISCADD_R,
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ISCADD_IMM,
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@ -489,10 +492,10 @@ public:
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enum class Type {
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Trivial,
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Arithmetic,
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ArithmeticInteger,
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Bfe,
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Logic,
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Shift,
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ScaledAdd,
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Ffma,
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Flow,
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Memory,
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@ -617,9 +620,12 @@ private:
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
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INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"),
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INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"),
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INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"),
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INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"),
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INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"),
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INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"),
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INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
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INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
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INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -992,13 +992,13 @@ private:
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break;
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}
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case OpCode::Type::ScaledAdd: {
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case OpCode::Type::ArithmeticInteger: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
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if (instr.iscadd.negate_a)
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if (instr.alu_integer.negate_a)
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op_a = '-' + op_a;
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std::string op_b = instr.iscadd.negate_b ? "-" : "";
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std::string op_b = instr.alu_integer.negate_b ? "-" : "";
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if (instr.is_b_imm) {
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op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
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@ -1011,10 +1011,30 @@ private:
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}
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}
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std::string shift = std::to_string(instr.iscadd.shift_amount.Value());
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switch (opcode->GetId()) {
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case OpCode::Id::IADD_C:
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case OpCode::Id::IADD_R:
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case OpCode::Id::IADD_IMM: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1);
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break;
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}
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case OpCode::Id::ISCADD_C:
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case OpCode::Id::ISCADD_R:
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case OpCode::Id::ISCADD_IMM: {
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std::string shift = std::to_string(instr.alu_integer.shift_amount.Value());
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
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break;
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}
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticInteger instruction: {}",
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opcode->GetName());
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UNREACHABLE();
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}
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}
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
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break;
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}
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case OpCode::Type::Ffma: {
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