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Merge pull request #399 from bunnei/shader-ints
Shader decompiler prep for integer instructions
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commit
bc43946140
@ -19,7 +19,10 @@ namespace Tegra {
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namespace Shader {
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struct Register {
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// Register 255 is special cased to always be 0
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/// Number of registers
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static constexpr size_t NumRegisters = 256;
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/// Register 255 is special cased to always be 0
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static constexpr size_t ZeroIndex = 255;
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constexpr Register() = default;
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@ -48,6 +51,11 @@ struct Register {
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return ~value;
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}
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u64 GetSwizzledIndex(u64 elem) const {
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elem = (value + elem) & 3;
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return (value & ~3) + elem;
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}
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private:
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u64 value{};
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};
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@ -146,6 +146,90 @@ private:
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std::string shader_source;
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};
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/**
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* Represents an emulated shader register, used to track the state of that register for emulation
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* with GLSL. At this time, a register can be used as a float or an integer. This class is used for
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* bookkeeping within the GLSL program.
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*/
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class GLSLRegister {
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public:
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GLSLRegister(size_t index, ShaderWriter& shader)
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: index{index}, shader{shader}, float_str{"freg_" + std::to_string(index)},
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integer_str{"ireg_" + std::to_string(index)} {}
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/// Returns a GLSL string representing the current state of the register
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const std::string& GetActiveString() {
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declr_type.insert(active_type);
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switch (active_type) {
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case Type::Float:
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return float_str;
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case Type::Integer:
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return integer_str;
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}
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UNREACHABLE();
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return float_str;
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}
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/// Returns a GLSL string representing the register as a float
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const std::string& GetFloatString() const {
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ASSERT(IsFloatUsed());
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return float_str;
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}
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/// Returns a GLSL string representing the register as an integer
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const std::string& GetIntegerString() const {
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ASSERT(IsIntegerUsed());
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return integer_str;
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}
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/// Convert the current register state from float to integer
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void FloatToInteger() {
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ASSERT(active_type == Type::Float);
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const std::string src = GetActiveString();
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active_type = Type::Integer;
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const std::string dest = GetActiveString();
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shader.AddLine(dest + " = floatBitsToInt(" + src + ");");
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}
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/// Convert the current register state from integer to float
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void IntegerToFloat() {
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ASSERT(active_type == Type::Integer);
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const std::string src = GetActiveString();
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active_type = Type::Float;
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const std::string dest = GetActiveString();
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shader.AddLine(dest + " = intBitsToFloat(" + src + ");");
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}
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/// Returns true if the register was ever used as a float, used for register declarations
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bool IsFloatUsed() const {
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return declr_type.find(Type::Float) != declr_type.end();
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}
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/// Returns true if the register was ever used as an integer, used for register declarations
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bool IsIntegerUsed() const {
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return declr_type.find(Type::Integer) != declr_type.end();
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}
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private:
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enum class Type {
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Float,
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Integer,
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};
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const size_t index;
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const std::string float_str;
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const std::string integer_str;
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ShaderWriter& shader;
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Type active_type{Type::Float};
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std::set<Type> declr_type;
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};
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class GLSLGenerator {
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public:
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GLSLGenerator(const std::set<Subroutine>& subroutines, const ProgramCode& program_code,
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@ -153,6 +237,7 @@ public:
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage) {
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BuildRegisterList();
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Generate();
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}
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@ -166,6 +251,13 @@ public:
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}
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private:
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/// Build the GLSL register list
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void BuildRegisterList() {
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for (size_t index = 0; index < Register::NumRegisters; ++index) {
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regs.emplace_back(index, shader);
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}
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}
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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auto iter = subroutines.find(Subroutine{begin, end});
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@ -221,14 +313,11 @@ private:
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (reg == Register::ZeroIndex)
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if (reg == Register::ZeroIndex) {
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return "0";
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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// GPRs 0-3 are output color for the fragment shader
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return std::string{"color."} + "rgba"[(reg + elem) & 3];
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}
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return *declr_register.insert("register_" + std::to_string(reg + elem)).first;
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return regs[reg.GetSwizzledIndex(elem)].GetActiveString();
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}
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/// Generates code representing a uniform (C buffer) register.
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@ -628,6 +717,15 @@ private:
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case OpCode::Id::EXIT: {
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ASSERT_MSG(instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex),
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"Predicated exits not implemented");
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// Final color output is currently hardcoded to GPR0-3 for fragment shaders
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
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shader.AddLine("color.r = " + GetRegister(0) + ";");
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shader.AddLine("color.g = " + GetRegister(1) + ";");
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shader.AddLine("color.b = " + GetRegister(2) + ";");
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shader.AddLine("color.a = " + GetRegister(3) + ";");
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}
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shader.AddLine("return true;");
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offset = PROGRAM_END - 1;
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break;
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@ -755,8 +853,13 @@ private:
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/// Add declarations for registers
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void GenerateDeclarations() {
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for (const auto& reg : declr_register) {
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declarations.AddLine("float " + reg + " = 0.0;");
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for (const auto& reg : regs) {
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if (reg.IsFloatUsed()) {
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declarations.AddLine("float " + reg.GetFloatString() + " = 0.0;");
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}
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if (reg.IsIntegerUsed()) {
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declarations.AddLine("int " + reg.GetIntegerString() + " = 0;");
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}
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}
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declarations.AddNewLine();
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@ -803,9 +906,9 @@ private:
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ShaderWriter shader;
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ShaderWriter declarations;
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std::vector<GLSLRegister> regs;
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// Declarations
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std::set<std::string> declr_register;
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std::set<std::string> declr_predicates;
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std::set<Attribute::Index> declr_input_attribute;
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std::set<Attribute::Index> declr_output_attribute;
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