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dyncom: Move exclusive load/stores above bbl and swi in the decoding table
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@ -190,12 +190,12 @@ const ISEITEM arm_instruction[] = {
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{ "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
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{ "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
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{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
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{ "swi", 1, 0, 24, 27, 0x0000000f },
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{ "bbl", 1, 0, 25, 27, 0x00000005 },
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{ "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
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{ "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
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{ "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
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{ "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
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{ "swi", 1, 0, 24, 27, 0x0000000f },
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{ "bbl", 1, 0, 25, 27, 0x00000005 },
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};
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const ISEITEM arm_exclusion_code[] = {
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@ -383,12 +383,12 @@ const ISEITEM arm_exclusion_code[] = {
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{ "cdp", 0, 0, 0 },
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{ "stc", 0, 0, 0 },
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{ "ldc", 0, 0, 0 },
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{ "swi", 0, 0, 0 },
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{ "bbl", 0, 0, 0 },
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{ "ldrexd", 0, ARMV6K, 0 },
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{ "strexd", 0, ARMV6K, 0 },
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{ "ldrexh", 0, ARMV6K, 0 },
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{ "strexh", 0, ARMV6K, 0 },
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{ "swi", 0, 0, 0 },
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{ "bbl", 0, 0, 0 },
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{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
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{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
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@ -3544,12 +3544,12 @@ const transop_fp_t arm_instruction_trans[] = {
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INTERPRETER_TRANSLATE(cdp),
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INTERPRETER_TRANSLATE(stc),
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INTERPRETER_TRANSLATE(ldc),
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INTERPRETER_TRANSLATE(swi),
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INTERPRETER_TRANSLATE(bbl),
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INTERPRETER_TRANSLATE(ldrexd),
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INTERPRETER_TRANSLATE(strexd),
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INTERPRETER_TRANSLATE(ldrexh),
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INTERPRETER_TRANSLATE(strexh),
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INTERPRETER_TRANSLATE(swi),
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INTERPRETER_TRANSLATE(bbl),
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// All the thumb instructions should be placed the end of table
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INTERPRETER_TRANSLATE(b_2_thumb),
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@ -3920,12 +3920,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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case 180: goto CDP_INST; \
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case 181: goto STC_INST; \
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case 182: goto LDC_INST; \
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case 183: goto SWI_INST; \
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case 184: goto BBL_INST; \
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case 185: goto LDREXD_INST; \
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case 186: goto STREXD_INST; \
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case 187: goto LDREXH_INST; \
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case 188: goto STREXH_INST; \
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case 183: goto LDREXD_INST; \
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case 184: goto STREXD_INST; \
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case 185: goto LDREXH_INST; \
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case 186: goto STREXH_INST; \
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case 187: goto SWI_INST; \
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case 188: goto BBL_INST; \
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case 189: goto B_2_THUMB ; \
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case 190: goto B_COND_THUMB ; \
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case 191: goto BL_1_THUMB ; \
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@ -3980,8 +3980,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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&&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
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&&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
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&&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
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&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST,
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&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
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&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST,
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&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&SWI_INST,&&BBL_INST,
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&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
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&&INIT_INST_LENGTH,&&END
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};
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#endif
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