diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 4e73cc03a1..56836bd051 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -86,6 +86,26 @@ public:
                   num_instructions, MemoryReadCode(pc));
     }
 
+    void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
+                                         VAddr value) override {
+        switch (op) {
+        case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
+            static constexpr u64 ICACHE_LINE_SIZE = 64;
+
+            const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
+            parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+            break;
+        }
+        case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
+            parent.ClearInstructionCache();
+            break;
+        case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
+        default:
+            LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
+            break;
+        }
+    }
+
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
         switch (exception) {
         case Dynarmic::A64::Exception::WaitForInterrupt: