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shader: Make IMNMX, SHR, SEL stylistically more consistent
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@ -23,7 +23,7 @@ void IMNMX(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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throw NotImplementedException("IMNMX.MODE");
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}
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IR::U1 pred = v.ir.GetPred(imnmx.pred);
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IR::U1 pred{v.ir.GetPred(imnmx.pred)};
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const IR::U32 op_a{v.X(imnmx.src_reg)};
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IR::U32 min;
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IR::U32 max;
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@ -16,7 +16,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
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BitField<39, 1, u64> is_wrapped;
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BitField<40, 1, u64> brev;
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BitField<43, 1, u64> xmode;
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BitField<48, 1, u64> is_arithmetic;
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BitField<48, 1, u64> is_signed;
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} const shr{insn};
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if (shr.xmode != 0) {
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@ -29,7 +29,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
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}
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IR::U32 result;
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const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
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if (shr.is_arithmetic == 1) {
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if (shr.is_signed == 1) {
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result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
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} else {
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result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
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@ -13,13 +13,13 @@ void SEL(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> op_a;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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} const sel{insn};
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const IR::U1 pred = v.ir.GetPred(sel.pred);
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IR::U32 op_a{v.X(sel.op_a)};
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IR::U32 op_a{v.X(sel.src_reg)};
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IR::U32 op_b{src};
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if (sel.neg_pred != 0) {
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std::swap(op_a, op_b);
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