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gl_shader_decompiler: Implement SHL instruction.
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@ -230,22 +230,19 @@ union Instruction {
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std::memcpy(&result, &imm, sizeof(imm));
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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return result;
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}
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}
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} alu;
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union {
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s32 GetSignedImm20_20() const {
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BitField<39, 5, u64> shift_amount;
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u32 immediate = static_cast<u32>(imm20_19 | (negate_imm << 19));
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BitField<20, 19, u64> immediate_low;
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BitField<56, 1, u64> immediate_high;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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s32 GetImmediate() const {
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u32 immediate = static_cast<u32>(immediate_low | (immediate_high << 19));
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// Sign extend the 20-bit value.
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// Sign extend the 20-bit value.
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u32 mask = 1U << (20 - 1);
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u32 mask = 1U << (20 - 1);
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return static_cast<s32>((immediate ^ mask) - mask);
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return static_cast<s32>((immediate ^ mask) - mask);
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}
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}
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} alu;
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union {
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BitField<39, 5, u64> shift_amount;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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} iscadd;
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} iscadd;
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union {
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union {
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@ -402,6 +399,9 @@ public:
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MOV_R,
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MOV_R,
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MOV_IMM,
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MOV_IMM,
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MOV32_IMM,
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MOV32_IMM,
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SHL_C,
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SHL_R,
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SHL_IMM,
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SHR_C,
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SHR_C,
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SHR_R,
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SHR_R,
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SHR_IMM,
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SHR_IMM,
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@ -424,6 +424,7 @@ public:
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Trivial,
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Trivial,
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Arithmetic,
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Arithmetic,
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Logic,
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Logic,
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Shift,
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ScaledAdd,
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ScaledAdd,
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Ffma,
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Ffma,
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Flow,
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Flow,
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@ -565,13 +566,16 @@ private:
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
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INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
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INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
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INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
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INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
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INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
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INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
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INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
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INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
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INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
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INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
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INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
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INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
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INST("0011100-01001---", Id::SHL_IMM, Type::Shift, "SHL_IMM"),
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INST("0100110000101---", Id::SHR_C, Type::Shift, "SHR_C"),
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INST("0101110000101---", Id::SHR_R, Type::Shift, "SHR_R"),
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INST("0011100-00101---", Id::SHR_IMM, Type::Shift, "SHR_IMM"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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@ -884,6 +884,35 @@ private:
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}
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}
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break;
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break;
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}
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}
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case OpCode::Type::Shift: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, false);
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std::string op_b;
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if (instr.is_b_imm) {
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op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
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} else {
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
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}
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}
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switch (opcode->GetId()) {
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case OpCode::Id::SHL_C:
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case OpCode::Id::SHL_R:
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case OpCode::Id::SHL_IMM:
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regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " << " + op_b, 1, 1);
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break;
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled shift instruction: {}", opcode->GetName());
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UNREACHABLE();
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}
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}
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break;
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}
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case OpCode::Type::ScaledAdd: {
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case OpCode::Type::ScaledAdd: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
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@ -893,7 +922,7 @@ private:
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std::string op_b = instr.iscadd.negate_b ? "-" : "";
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std::string op_b = instr.iscadd.negate_b ? "-" : "";
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if (instr.is_b_imm) {
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if (instr.is_b_imm) {
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op_b += '(' + std::to_string(instr.iscadd.GetImmediate()) + ')';
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op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
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} else {
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} else {
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if (instr.is_b_gpr) {
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20);
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op_b += regs.GetRegisterAsInteger(instr.gpr20);
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