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https://github.com/yuzu-emu/yuzu.git
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shader: Implement DMUL and DFMA
Also add a missing const on DADD
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@ -65,6 +65,8 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/condition_code_set.cpp
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frontend/maxwell/translate/impl/double_add.cpp
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frontend/maxwell/translate/impl/double_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/double_multiply.cpp
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frontend/maxwell/translate/impl/exit_program.cpp
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frontend/maxwell/translate/impl/find_leading_one.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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@ -35,7 +35,7 @@ INST(DADD_imm, "DADD (imm)", "0011 100- 0111 0---")
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INST(DEPBAR, "DEPBAR", "1111 0000 1111 0---")
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INST(DFMA_reg, "DFMA (reg)", "0101 1011 0111 ----")
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INST(DFMA_rc, "DFMA (rc)", "0101 0011 0111 ----")
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INST(DFMA_cr, "DFMA (cr)", "0010 1011 0111 ----")
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INST(DFMA_cr, "DFMA (cr)", "0100 1011 0111 ----")
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INST(DFMA_imm, "DFMA (imm)", "0011 011- 0111 ----")
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INST(DMNMX_reg, "DMNMX (reg)", "0100 1100 0101 0---")
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INST(DMNMX_cbuf, "DMNMX (cbuf)", "0101 1100 0101 0---")
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@ -30,7 +30,7 @@ void DADD(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
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const IR::F64 op_a{v.ir.FPAbsNeg(src_a, dadd.abs_a != 0, dadd.neg_a != 0)};
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const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dadd.abs_b != 0, dadd.neg_b != 0)};
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IR::FpControl control{
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const IR::FpControl control{
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.no_contraction{true},
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.rounding{CastFpRounding(dadd.fp_rounding)},
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.fmz_mode{IR::FmzMode::None},
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@ -0,0 +1,53 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void DFMA(TranslatorVisitor& v, u64 insn, const IR::F64& src_b, const IR::F64& src_c) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<50, 2, FpRounding> fp_rounding;
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BitField<48, 1, u64> neg_b;
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BitField<49, 1, u64> neg_c;
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} const dfma{insn};
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const IR::F64 src_a{v.D(dfma.src_a_reg)};
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const IR::F64 op_b{v.ir.FPAbsNeg(src_b, false, dfma.neg_b != 0)};
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const IR::F64 op_c{v.ir.FPAbsNeg(src_c, false, dfma.neg_c != 0)};
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const IR::FpControl control{
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.no_contraction{true},
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.rounding{CastFpRounding(dfma.fp_rounding)},
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.fmz_mode{IR::FmzMode::None},
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};
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v.D(dfma.dest_reg, v.ir.FPFma(src_a, op_b, op_c, control));
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}
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} // Anonymous namespace
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void TranslatorVisitor::DFMA_reg(u64 insn) {
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DFMA(*this, insn, GetDoubleReg20(insn), GetDoubleReg39(insn));
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}
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void TranslatorVisitor::DFMA_cr(u64 insn) {
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DFMA(*this, insn, GetDoubleCbuf(insn), GetDoubleReg39(insn));
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}
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void TranslatorVisitor::DFMA_rc(u64 insn) {
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DFMA(*this, insn, GetDoubleReg39(insn), GetDoubleCbuf(insn));
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}
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void TranslatorVisitor::DFMA_imm(u64 insn) {
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DFMA(*this, insn, GetDoubleImm20(insn), GetDoubleReg39(insn));
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}
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} // namespace Shader::Maxwell
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@ -0,0 +1,45 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void DMUL(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<39, 2, FpRounding> fp_rounding;
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BitField<48, 1, u64> neg;
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} const dmul{insn};
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const IR::F64 src_a{v.ir.FPAbsNeg(v.D(dmul.src_a_reg), false, dmul.neg != 0)};
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const IR::FpControl control{
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.no_contraction{true},
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.rounding{CastFpRounding(dmul.fp_rounding)},
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.fmz_mode{IR::FmzMode::None},
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};
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v.D(dmul.dest_reg, v.ir.FPMul(src_a, src_b, control));
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}
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} // Anonymous namespace
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void TranslatorVisitor::DMUL_reg(u64 insn) {
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DMUL(*this, insn, GetDoubleReg20(insn));
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}
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void TranslatorVisitor::DMUL_cbuf(u64 insn) {
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DMUL(*this, insn, GetDoubleCbuf(insn));
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}
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void TranslatorVisitor::DMUL_imm(u64 insn) {
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DMUL(*this, insn, GetDoubleImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -90,6 +90,14 @@ IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) {
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return D(reg.index);
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}
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IR::F64 TranslatorVisitor::GetDoubleReg39(u64 insn) {
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union {
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u64 raw;
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BitField<39, 8, IR::Reg> index;
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} const reg{insn};
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return D(reg.index);
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}
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static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {
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union {
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u64 raw;
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@ -354,6 +354,7 @@ public:
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[[nodiscard]] IR::F32 GetFloatReg20(u64 insn);
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[[nodiscard]] IR::F32 GetFloatReg39(u64 insn);
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[[nodiscard]] IR::F64 GetDoubleReg20(u64 insn);
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[[nodiscard]] IR::F64 GetDoubleReg39(u64 insn);
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[[nodiscard]] IR::U32 GetCbuf(u64 insn);
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[[nodiscard]] IR::F32 GetFloatCbuf(u64 insn);
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@ -81,22 +81,6 @@ void TranslatorVisitor::DEPBAR() {
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// DEPBAR is a no-op
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}
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void TranslatorVisitor::DFMA_reg(u64) {
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ThrowNotImplemented(Opcode::DFMA_reg);
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}
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void TranslatorVisitor::DFMA_rc(u64) {
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ThrowNotImplemented(Opcode::DFMA_rc);
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}
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void TranslatorVisitor::DFMA_cr(u64) {
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ThrowNotImplemented(Opcode::DFMA_cr);
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}
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void TranslatorVisitor::DFMA_imm(u64) {
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ThrowNotImplemented(Opcode::DFMA_imm);
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}
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void TranslatorVisitor::DMNMX_reg(u64) {
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ThrowNotImplemented(Opcode::DMNMX_reg);
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}
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@ -109,18 +93,6 @@ void TranslatorVisitor::DMNMX_imm(u64) {
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ThrowNotImplemented(Opcode::DMNMX_imm);
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}
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void TranslatorVisitor::DMUL_reg(u64) {
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ThrowNotImplemented(Opcode::DMUL_reg);
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}
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void TranslatorVisitor::DMUL_cbuf(u64) {
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ThrowNotImplemented(Opcode::DMUL_cbuf);
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}
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void TranslatorVisitor::DMUL_imm(u64) {
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ThrowNotImplemented(Opcode::DMUL_imm);
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}
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void TranslatorVisitor::DSET_reg(u64) {
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ThrowNotImplemented(Opcode::DSET_reg);
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}
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