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Merge pull request #609 from Subv/clear_buffers
GPU: Implemented the CLEAR_BUFFERS register.
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commit
c996787d84
@ -126,6 +126,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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DrawArrays();
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break;
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}
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case MAXWELL3D_REG_INDEX(clear_buffers): {
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ProcessClearBuffers();
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break;
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}
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case MAXWELL3D_REG_INDEX(query.query_get): {
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ProcessQueryGet();
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break;
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@ -415,5 +419,13 @@ bool Maxwell3D::IsShaderStageEnabled(Regs::ShaderStage stage) const {
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UNREACHABLE();
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}
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void Maxwell3D::ProcessClearBuffers() {
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ASSERT(regs.clear_buffers.R == regs.clear_buffers.G &&
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regs.clear_buffers.R == regs.clear_buffers.B &&
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regs.clear_buffers.R == regs.clear_buffers.A);
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VideoCore::g_renderer->Rasterizer()->Clear();
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}
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} // namespace Engines
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} // namespace Tegra
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@ -436,7 +436,12 @@ public:
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u32 count;
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} vertex_buffer;
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INSERT_PADDING_WORDS(0x99);
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INSERT_PADDING_WORDS(1);
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float clear_color[4];
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float clear_depth;
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INSERT_PADDING_WORDS(0x93);
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struct {
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u32 address_high;
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@ -584,7 +589,21 @@ public:
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Cull cull;
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INSERT_PADDING_WORDS(0x77);
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INSERT_PADDING_WORDS(0x2B);
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union {
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u32 raw;
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BitField<0, 1, u32> Z;
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BitField<1, 1, u32> S;
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BitField<2, 1, u32> R;
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BitField<3, 1, u32> G;
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BitField<4, 1, u32> B;
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BitField<5, 1, u32> A;
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BitField<6, 4, u32> RT;
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BitField<10, 11, u32> layer;
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} clear_buffers;
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INSERT_PADDING_WORDS(0x4B);
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struct {
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u32 query_address_high;
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@ -766,6 +785,9 @@ private:
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/// Handles writes to the macro uploading registers.
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void ProcessMacroUpload(u32 data);
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/// Handles a write to the CLEAR_BUFFERS register.
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void ProcessClearBuffers();
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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@ -788,6 +810,8 @@ ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(viewport_transform[0], 0x280);
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ASSERT_REG_POSITION(viewport, 0x300);
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ASSERT_REG_POSITION(vertex_buffer, 0x35D);
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ASSERT_REG_POSITION(clear_color[0], 0x360);
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ASSERT_REG_POSITION(clear_depth, 0x364);
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ASSERT_REG_POSITION(zeta, 0x3F8);
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ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
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ASSERT_REG_POSITION(rt_control, 0x487);
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@ -803,6 +827,7 @@ ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(index_array, 0x5F2);
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ASSERT_REG_POSITION(cull, 0x646);
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ASSERT_REG_POSITION(clear_buffers, 0x674);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(independent_blend, 0x780);
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@ -19,6 +19,9 @@ public:
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/// Draw the current batch of vertex arrays
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virtual void DrawArrays() = 0;
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/// Clear the current framebuffer
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virtual void Clear() = 0;
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/// Notify rasterizer that the specified Maxwell register has been changed
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virtual void NotifyMaxwellRegisterChanged(u32 method) = 0;
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@ -297,11 +297,7 @@ bool RasterizerOpenGL::AccelerateDrawBatch(bool is_indexed) {
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return true;
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}
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void RasterizerOpenGL::DrawArrays() {
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if (accelerate_draw == AccelDraw::Disabled)
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return;
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MICROPROFILE_SCOPE(OpenGL_Drawing);
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std::pair<Surface, Surface> RasterizerOpenGL::ConfigureFramebuffers() {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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// Sync the depth test state before configuring the framebuffer surfaces.
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@ -344,11 +340,6 @@ void RasterizerOpenGL::DrawArrays() {
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BindFramebufferSurfaces(color_surface, depth_surface, has_stencil);
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SyncViewport(surfaces_rect);
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SyncBlendState();
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SyncCullMode();
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// TODO(bunnei): Sync framebuffer_scale uniform here
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// TODO(bunnei): Sync scissorbox uniform(s) here
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// Viewport can have negative offsets or larger dimensions than our framebuffer sub-rect. Enable
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// scissor test to prevent drawing outside of the framebuffer region
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@ -359,6 +350,58 @@ void RasterizerOpenGL::DrawArrays() {
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state.scissor.height = draw_rect.GetHeight();
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state.Apply();
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// Only return the surface to be marked as dirty if writing to it is enabled.
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return std::make_pair(write_color_fb ? color_surface : nullptr,
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write_depth_fb ? depth_surface : nullptr);
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}
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void RasterizerOpenGL::Clear() {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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GLbitfield clear_mask = 0;
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if (regs.clear_buffers.R && regs.clear_buffers.G && regs.clear_buffers.B &&
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regs.clear_buffers.A) {
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clear_mask |= GL_COLOR_BUFFER_BIT;
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}
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if (regs.clear_buffers.Z)
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clear_mask |= GL_DEPTH_BUFFER_BIT;
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if (clear_mask == 0)
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return;
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auto [dirty_color_surface, dirty_depth_surface] = ConfigureFramebuffers();
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// TODO(Subv): Support clearing only partial colors.
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glClearColor(regs.clear_color[0], regs.clear_color[1], regs.clear_color[2],
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regs.clear_color[3]);
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glClearDepth(regs.clear_depth);
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glClear(clear_mask);
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// Mark framebuffer surfaces as dirty
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if (dirty_color_surface != nullptr) {
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res_cache.MarkSurfaceAsDirty(dirty_color_surface);
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}
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if (dirty_depth_surface != nullptr) {
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res_cache.MarkSurfaceAsDirty(dirty_depth_surface);
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}
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}
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void RasterizerOpenGL::DrawArrays() {
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if (accelerate_draw == AccelDraw::Disabled)
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return;
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MICROPROFILE_SCOPE(OpenGL_Drawing);
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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auto [dirty_color_surface, dirty_depth_surface] = ConfigureFramebuffers();
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SyncBlendState();
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SyncCullMode();
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// TODO(bunnei): Sync framebuffer_scale uniform here
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// TODO(bunnei): Sync scissorbox uniform(s) here
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// Draw the vertex batch
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const bool is_indexed = accelerate_draw == AccelDraw::Indexed;
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const u64 index_buffer_size{regs.index_array.count * regs.index_array.FormatSizeInBytes()};
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@ -439,11 +482,11 @@ void RasterizerOpenGL::DrawArrays() {
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state.Apply();
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// Mark framebuffer surfaces as dirty
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if (color_surface != nullptr && write_color_fb) {
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res_cache.MarkSurfaceAsDirty(color_surface);
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if (dirty_color_surface != nullptr) {
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res_cache.MarkSurfaceAsDirty(dirty_color_surface);
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}
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if (depth_surface != nullptr && write_depth_fb) {
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res_cache.MarkSurfaceAsDirty(depth_surface);
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if (dirty_depth_surface != nullptr) {
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res_cache.MarkSurfaceAsDirty(dirty_depth_surface);
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}
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}
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@ -7,6 +7,7 @@
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#include <array>
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#include <cstddef>
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#include <memory>
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#include <utility>
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#include <vector>
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#include <glad/glad.h>
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#include "common/common_types.h"
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@ -28,6 +29,7 @@ public:
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~RasterizerOpenGL() override;
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void DrawArrays() override;
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void Clear() override;
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void NotifyMaxwellRegisterChanged(u32 method) override;
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void FlushAll() override;
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void FlushRegion(Tegra::GPUVAddr addr, u64 size) override;
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@ -81,6 +83,10 @@ private:
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u32 border_color_a;
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};
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/// Configures the color and depth framebuffer states and returns the dirty <Color, Depth>
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/// surfaces if writing was enabled.
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std::pair<Surface, Surface> ConfigureFramebuffers();
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/// Binds the framebuffer color and depth surface
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void BindFramebufferSurfaces(const Surface& color_surface, const Surface& depth_surface,
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bool has_stencil);
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