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GSP: Implement ReadHWRegs and WriteHWRegs properly.
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@ -47,11 +47,6 @@ Handle g_shared_memory = 0;
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u32 g_thread_id = 0;
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enum {
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REG_FRAMEBUFFER_1 = 0x00400468,
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REG_FRAMEBUFFER_2 = 0x00400494,
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};
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/// Gets a pointer to the start (header) of a command buffer in GSP shared memory
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static inline u8* GX_GetCmdBufferPointer(u32 thread_id, u32 offset=0) {
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return Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * 0x200) + offset);
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@ -67,38 +62,62 @@ void GX_FinishCommand(u32 thread_id) {
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// TODO: Increment header->index?
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}
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/// Read a GSP GPU hardware register
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void ReadHWRegs(Service::Interface* self) {
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static const u32 framebuffer_1[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME1, GPU::PADDR_VRAM_TOP_RIGHT_FRAME1};
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static const u32 framebuffer_2[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME2, GPU::PADDR_VRAM_TOP_RIGHT_FRAME2};
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/// Write a GSP GPU hardware register
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void WriteHWRegs(Service::Interface* self) {
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u32* cmd_buff = Service::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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switch (reg_addr) {
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// NOTE: Calling SetFramebufferLocation here is a hack... Not sure the correct way yet to set
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// whether the framebuffers should be in VRAM or GSP heap, but from what I understand, if the
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// user application is reading from either of these registers, then its going to be in VRAM.
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// Top framebuffer 1 addresses
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case REG_FRAMEBUFFER_1:
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GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
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memcpy(dst, framebuffer_1, size);
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break;
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// Top framebuffer 2 addresses
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case REG_FRAMEBUFFER_2:
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GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM);
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memcpy(dst, framebuffer_2, size);
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break;
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default:
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ERROR_LOG(GSP, "unknown register read at address %08X", reg_addr);
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Write address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
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while (size > 0) {
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GPU::Write<u32>(reg_addr + 0x1EB00000, *src);
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size -= 4;
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++src;
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reg_addr += 4;
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}
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}
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/// Read a GSP GPU hardware register
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void ReadHWRegs(Service::Interface* self) {
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u32* cmd_buff = Service::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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while (size > 0) {
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GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
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size -= 4;
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++dst;
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reg_addr += 4;
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}
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}
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/**
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@ -179,7 +198,7 @@ void TriggerCmdReqQueue(Service::Interface* self) {
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}
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const Interface::FunctionInfo FunctionTable[] = {
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{0x00010082, nullptr, "WriteHWRegs"},
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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{0x00020084, nullptr, "WriteHWRegsWithMask"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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