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shader: Implement SHR
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@ -72,6 +72,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/integer_scaled_add.cpp
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frontend/maxwell/translate/impl/integer_set_predicate.cpp
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frontend/maxwell/translate/impl/integer_shift_left.cpp
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frontend/maxwell/translate/impl/integer_shift_right.cpp
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frontend/maxwell/translate/impl/integer_short_multiply_add.cpp
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frontend/maxwell/translate/impl/load_store_attribute.cpp
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frontend/maxwell/translate/impl/load_store_memory.cpp
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@ -219,14 +219,15 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b);
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Id EmitINeg32(EmitContext& ctx, Id value);
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Id EmitIAbs32(EmitContext& ctx, Id value);
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
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void EmitShiftRightLogical32(EmitContext& ctx);
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void EmitShiftRightArithmetic32(EmitContext& ctx);
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Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
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Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
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Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
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@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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}
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void EmitShiftRightLogical32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
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}
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void EmitShiftRightArithmetic32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
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}
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
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@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
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}
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Id EmitBitReverse32(EmitContext& ctx, Id value) {
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return ctx.OpBitReverse(ctx.U32[1], value);
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}
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1, lhs, rhs);
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}
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@ -804,6 +804,10 @@ U32 IREmitter::BitFieldExtract(const U32& base, const U32& offset, const U32& co
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count);
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}
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U32 IREmitter::BitReverse(const U32& value) {
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return Inst<U32>(Opcode::BitReverse32, value);
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}
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U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
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return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
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}
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@ -159,6 +159,7 @@ public:
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const U32& count);
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[[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
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bool is_signed);
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[[nodiscard]] U32 BitReverse(const U32& value);
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[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
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[[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);
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@ -231,6 +231,7 @@ OPCODE(BitwiseXor32, U32, U32,
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OPCODE(BitFieldInsert, U32, U32, U32, U32, U32, )
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OPCODE(BitFieldSExtract, U32, U32, U32, U32, )
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OPCODE(BitFieldUExtract, U32, U32, U32, U32, )
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OPCODE(BitReverse32, U32, U32, )
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OPCODE(SLessThan, U1, U32, U32, )
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OPCODE(ULessThan, U1, U32, U32, )
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@ -0,0 +1,62 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<39, 1, u64> is_wrapped;
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BitField<40, 1, u64> brev;
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BitField<43, 1, u64> xmode;
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BitField<48, 1, u64> is_arithmetic;
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} const shr{insn};
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if (shr.xmode != 0) {
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throw NotImplementedException("SHR.XMODE");
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}
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IR::U32 base{v.X(shr.src_reg_a)};
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if (shr.brev == 1) {
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base = v.ir.BitReverse(base);
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}
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IR::U32 result;
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const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
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if (shr.is_arithmetic == 1) {
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result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
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} else {
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result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
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}
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if (shr.is_wrapped == 0) {
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const IR::U32 zero{v.ir.Imm32(0)};
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const IR::U32 safe_bits{v.ir.Imm32(32)};
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const IR::U1 is_negative{v.ir.ILessThan(result, zero, true)};
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const IR::U1 is_safe{v.ir.ILessThan(shift, safe_bits, false)};
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const IR::U32 clamped_value{v.ir.Select(is_negative, v.ir.Imm32(-1), zero)};
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result = IR::U32{v.ir.Select(is_safe, result, clamped_value)};
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}
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v.X(shr.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SHR_reg(u64 insn) {
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SHR(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::SHR_cbuf(u64 insn) {
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SHR(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::SHR_imm(u64 insn) {
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SHR(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -757,18 +757,6 @@ void TranslatorVisitor::SHFL(u64) {
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ThrowNotImplemented(Opcode::SHFL);
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}
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void TranslatorVisitor::SHR_reg(u64) {
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ThrowNotImplemented(Opcode::SHR_reg);
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}
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void TranslatorVisitor::SHR_cbuf(u64) {
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ThrowNotImplemented(Opcode::SHR_cbuf);
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}
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void TranslatorVisitor::SHR_imm(u64) {
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ThrowNotImplemented(Opcode::SHR_imm);
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}
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void TranslatorVisitor::SSY() {
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// SSY is a no-op
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}
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