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Merge pull request #241 from Subv/gpu_method_call
GPU: Process command mode 5 (IncreaseOnce) differently from other commands
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commit
cd4e8a989c
@ -64,6 +64,35 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
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}
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}
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}
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}
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void GPU::CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters) {
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LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u num params %zu", method,
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subchannel, parameters.size());
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if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
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// TODO(Subv): Research and implement these methods.
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LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
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return;
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}
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ASSERT(bound_engines.find(subchannel) != bound_engines.end());
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const EngineID engine = bound_engines[subchannel];
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switch (engine) {
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case EngineID::FERMI_TWOD_A:
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fermi_2d->CallMethod(method, parameters);
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break;
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case EngineID::MAXWELL_B:
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maxwell_3d->CallMethod(method, parameters);
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break;
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case EngineID::MAXWELL_COMPUTE_B:
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maxwell_compute->CallMethod(method, parameters);
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break;
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default:
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UNIMPLEMENTED();
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}
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}
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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// TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
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// TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
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// application VAddr.
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// application VAddr.
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@ -96,13 +125,17 @@ void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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ASSERT(header.arg_count.Value() >= 1);
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ASSERT(header.arg_count.Value() >= 1);
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// Use the original method for the first argument and then the next method for all other
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// Use the original method for the first argument and then the next method for all other
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// arguments.
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// arguments.
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
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current_addr += sizeof(u32);
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// Process this command as a method call instead of a register write. Gather
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// Use the same method value for all arguments.
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// all the parameters first and then pass them at once to the CallMethod function.
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for (unsigned i = 1; i < header.arg_count; ++i) {
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std::vector<u32> parameters(header.arg_count);
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WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr));
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for (unsigned i = 0; i < header.arg_count; ++i) {
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parameters[i] = Memory::Read32(current_addr);
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current_addr += sizeof(u32);
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current_addr += sizeof(u32);
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}
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}
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CallMethod(header.method, header.subchannel, parameters);
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break;
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break;
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}
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}
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case SubmissionMode::Inline: {
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case SubmissionMode::Inline: {
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@ -34,6 +34,4 @@ static_assert(std::is_standard_layout<CommandHeader>::value == true,
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"CommandHeader does not use standard layout");
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"CommandHeader does not use standard layout");
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static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
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static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
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void ProcessCommandList(VAddr address, u32 size);
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} // namespace Tegra
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} // namespace Tegra
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@ -8,6 +8,7 @@ namespace Tegra {
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namespace Engines {
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namespace Engines {
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void Fermi2D::WriteReg(u32 method, u32 value) {}
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void Fermi2D::WriteReg(u32 method, u32 value) {}
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void Fermi2D::CallMethod(u32 method, const std::vector<u32>& parameters) {}
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} // namespace Engines
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} // namespace Engines
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} // namespace Tegra
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} // namespace Tegra
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@ -4,6 +4,7 @@
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#pragma once
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Tegra {
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@ -16,6 +17,13 @@ public:
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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void WriteReg(u32 method, u32 value);
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/**
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* Handles a method call to this engine.
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMethod(u32 method, const std::vector<u32>& parameters);
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};
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};
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} // namespace Engines
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} // namespace Engines
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@ -8,8 +8,23 @@
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namespace Tegra {
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namespace Tegra {
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namespace Engines {
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namespace Engines {
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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{0xE24, {"PrepareShader", 5, &Maxwell3D::PrepareShader}},
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
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auto itr = method_handlers.find(method);
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if (itr == method_handlers.end()) {
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LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
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return;
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}
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ASSERT(itr->second.arguments == parameters.size());
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(this->*itr->second.handler)(parameters);
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}
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void Maxwell3D::WriteReg(u32 method, u32 value) {
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void Maxwell3D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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@ -64,5 +79,7 @@ void Maxwell3D::DrawArrays() {
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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}
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}
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void Maxwell3D::PrepareShader(const std::vector<u32>& parameters) {}
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} // namespace Engines
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} // namespace Engines
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} // namespace Tegra
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} // namespace Tegra
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@ -4,6 +4,8 @@
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#pragma once
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#pragma once
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#include <unordered_map>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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@ -20,6 +22,13 @@ public:
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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void WriteReg(u32 method, u32 value);
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/**
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* Handles a method call to this engine.
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMethod(u32 method, const std::vector<u32>& parameters);
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/// Register structure of the Maxwell3D engine.
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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struct Regs {
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@ -112,13 +121,24 @@ public:
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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private:
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private:
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MemoryManager& memory_manager;
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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void DrawArrays();
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MemoryManager& memory_manager;
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/// Method call handlers
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void PrepareShader(const std::vector<u32>& parameters);
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struct MethodInfo {
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const char* name;
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u32 arguments;
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void (Maxwell3D::*handler)(const std::vector<u32>& parameters);
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};
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static const std::unordered_map<u32, MethodInfo> method_handlers;
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};
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -8,6 +8,7 @@ namespace Tegra {
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namespace Engines {
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namespace Engines {
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void MaxwellCompute::WriteReg(u32 method, u32 value) {}
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void MaxwellCompute::WriteReg(u32 method, u32 value) {}
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void MaxwellCompute::CallMethod(u32 method, const std::vector<u32>& parameters) {}
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} // namespace Engines
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} // namespace Engines
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} // namespace Tegra
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} // namespace Tegra
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@ -4,6 +4,7 @@
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#pragma once
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Tegra {
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@ -16,6 +17,13 @@ public:
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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void WriteReg(u32 method, u32 value);
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/**
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* Handles a method call to this engine.
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* @param method Method to call
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* @param parameters Arguments to the method call
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*/
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void CallMethod(u32 method, const std::vector<u32>& parameters);
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};
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};
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} // namespace Engines
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} // namespace Engines
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@ -41,6 +41,9 @@ private:
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/// Writes a single register in the engine bound to the specified subchannel
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/// Writes a single register in the engine bound to the specified subchannel
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void WriteReg(u32 method, u32 subchannel, u32 value);
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void WriteReg(u32 method, u32 subchannel, u32 value);
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/// Calls a method in the engine bound to the specified subchannel with the input parameters.
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void CallMethod(u32 method, u32 subchannel, const std::vector<u32>& parameters);
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/// Mapping of command subchannels to their bound engine ids.
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/// Mapping of command subchannels to their bound engine ids.
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std::unordered_map<u32, EngineID> bound_engines;
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std::unordered_map<u32, EngineID> bound_engines;
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