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https://github.com/yuzu-emu/yuzu.git
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Implement PSET, refactor common comparison funcs
This commit is contained in:
parent
103b9da4f7
commit
ce9b116cfe
@ -89,6 +89,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/predicate_set.cpp
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.h
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frontend/maxwell/translate/translate.h
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@ -5,42 +5,42 @@
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 IntegerCompare(TranslatorVisitor& v, const IR::U32& operand_1,
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, ComparisonOp compare_op,
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const IR::U32& operand_2, CompareOp compare_op,
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bool is_signed) {
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bool is_signed) {
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switch (compare_op) {
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switch (compare_op) {
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case ComparisonOp::False:
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case CompareOp::False:
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return v.ir.Imm1(false);
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return ir.Imm1(false);
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case ComparisonOp::LessThan:
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case CompareOp::LessThan:
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return v.ir.ILessThan(operand_1, operand_2, is_signed);
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return ir.ILessThan(operand_1, operand_2, is_signed);
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case ComparisonOp::Equal:
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case CompareOp::Equal:
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return v.ir.IEqual(operand_1, operand_2);
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return ir.IEqual(operand_1, operand_2);
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case ComparisonOp::LessThanEqual:
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case CompareOp::LessThanEqual:
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return v.ir.ILessThanEqual(operand_1, operand_2, is_signed);
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return ir.ILessThanEqual(operand_1, operand_2, is_signed);
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case ComparisonOp::GreaterThan:
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case CompareOp::GreaterThan:
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return v.ir.IGreaterThan(operand_1, operand_2, is_signed);
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return ir.IGreaterThan(operand_1, operand_2, is_signed);
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case ComparisonOp::NotEqual:
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case CompareOp::NotEqual:
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return v.ir.INotEqual(operand_1, operand_2);
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return ir.INotEqual(operand_1, operand_2);
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case ComparisonOp::GreaterThanEqual:
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case CompareOp::GreaterThanEqual:
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return v.ir.IGreaterThanEqual(operand_1, operand_2, is_signed);
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return ir.IGreaterThanEqual(operand_1, operand_2, is_signed);
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case ComparisonOp::True:
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case CompareOp::True:
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return v.ir.Imm1(true);
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return ir.Imm1(true);
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default:
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default:
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throw NotImplementedException("CMP");
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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}
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}
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[[nodiscard]] IR::U1 PredicateCombine(TranslatorVisitor& v, const IR::U1& predicate_1,
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop) {
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const IR::U1& predicate_2, BooleanOp bop) {
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switch (bop) {
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switch (bop) {
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case BooleanOp::And:
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case BooleanOp::AND:
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return v.ir.LogicalAnd(predicate_1, predicate_2);
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return ir.LogicalAnd(predicate_1, predicate_2);
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case BooleanOp::Or:
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case BooleanOp::OR:
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return v.ir.LogicalOr(predicate_1, predicate_2);
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return ir.LogicalOr(predicate_1, predicate_2);
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case BooleanOp::Xor:
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case BooleanOp::XOR:
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return v.ir.LogicalXor(predicate_1, predicate_2);
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return ir.LogicalXor(predicate_1, predicate_2);
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default:
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default:
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throw NotImplementedException("BOP");
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throw NotImplementedException("Invalid bop {}", bop);
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}
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}
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}
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}
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} // namespace Shader::Maxwell
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} // namespace Shader::Maxwell
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@ -8,10 +8,9 @@
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 IntegerCompare(TranslatorVisitor& v, const IR::U32& operand_1,
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, ComparisonOp compare_op,
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const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
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bool is_signed);
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[[nodiscard]] IR::U1 PredicateCombine(TranslatorVisitor& v, const IR::U1& predicate_1,
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop);
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const IR::U1& predicate_2, BooleanOp bop);
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} // namespace Shader::Maxwell
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} // namespace Shader::Maxwell
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@ -11,7 +11,7 @@
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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enum class ComparisonOp : u64 {
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enum class CompareOp : u64 {
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False,
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False,
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LessThan,
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LessThan,
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Equal,
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Equal,
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@ -23,9 +23,9 @@ enum class ComparisonOp : u64 {
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};
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};
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enum class BooleanOp : u64 {
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enum class BooleanOp : u64 {
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And,
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AND,
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Or,
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OR,
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Xor,
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XOR,
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};
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};
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class TranslatorVisitor {
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class TranslatorVisitor {
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@ -15,12 +15,12 @@ void ICMP(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::U32& o
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, ComparisonOp> compare_op;
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BitField<49, 3, CompareOp> compare_op;
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} const icmp{insn};
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} const icmp{insn};
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const IR::U32 zero{v.ir.Imm32(0)};
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const IR::U32 zero{v.ir.Imm32(0)};
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const bool is_signed{icmp.is_signed != 0};
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const bool is_signed{icmp.is_signed != 0};
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const IR::U1 cmp_result{IntegerCompare(v, operand, zero, icmp.compare_op, is_signed)};
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const IR::U1 cmp_result{IntegerCompare(v.ir, operand, zero, icmp.compare_op, is_signed)};
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const IR::U32 src_reg{v.X(icmp.src_reg)};
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const IR::U32 src_reg{v.X(icmp.src_reg)};
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const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};
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const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};
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@ -20,7 +20,7 @@ void ISET(TranslatorVisitor& v, u64 insn, const IR::U32& src_a) {
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BitField<44, 1, u64> bf;
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BitField<44, 1, u64> bf;
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BitField<45, 2, BooleanOp> bop;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, ComparisonOp> compare_op;
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BitField<49, 3, CompareOp> compare_op;
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} const iset{insn};
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} const iset{insn};
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if (iset.x != 0) {
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if (iset.x != 0) {
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@ -33,8 +33,8 @@ void ISET(TranslatorVisitor& v, u64 insn, const IR::U32& src_a) {
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if (iset.neg_pred != 0) {
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if (iset.neg_pred != 0) {
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pred = v.ir.LogicalNot(pred);
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pred = v.ir.LogicalNot(pred);
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}
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}
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const IR::U1 cmp_result{IntegerCompare(v, src_reg, src_a, iset.compare_op, is_signed)};
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const IR::U1 cmp_result{IntegerCompare(v.ir, src_reg, src_a, iset.compare_op, is_signed)};
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const IR::U1 bop_result{PredicateCombine(v, cmp_result, pred, iset.bop)};
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const IR::U1 bop_result{PredicateCombine(v.ir, cmp_result, pred, iset.bop)};
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const IR::U32 one_mask{v.ir.Imm32(-1)};
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const IR::U32 one_mask{v.ir.Imm32(-1)};
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const IR::U32 fp_one{v.ir.Imm32(0x3f800000)};
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const IR::U32 fp_one{v.ir.Imm32(0x3f800000)};
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@ -4,62 +4,11 @@
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#include "common/bit_field.h"
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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namespace {
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namespace {
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enum class CompareOp : u64 {
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F, // Always false
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LT, // Less than
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EQ, // Equal
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LE, // Less than or equal
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GT, // Greater than
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NE, // Not equal
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GE, // Greater than or equal
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T, // Always true
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};
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enum class Bop : u64 {
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AND,
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OR,
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XOR,
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};
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IR::U1 Compare(IR::IREmitter& ir, CompareOp op, const IR::U32& lhs, const IR::U32& rhs,
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bool is_signed) {
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switch (op) {
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case CompareOp::F:
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return ir.Imm1(false);
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case CompareOp::LT:
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return ir.ILessThan(lhs, rhs, is_signed);
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case CompareOp::EQ:
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return ir.IEqual(lhs, rhs);
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case CompareOp::LE:
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return ir.ILessThanEqual(lhs, rhs, is_signed);
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case CompareOp::GT:
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return ir.IGreaterThan(lhs, rhs, is_signed);
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case CompareOp::NE:
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return ir.INotEqual(lhs, rhs);
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case CompareOp::GE:
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return ir.IGreaterThanEqual(lhs, rhs, is_signed);
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case CompareOp::T:
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return ir.Imm1(true);
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}
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throw NotImplementedException("Invalid ISETP compare op {}", op);
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}
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IR::U1 Combine(IR::IREmitter& ir, Bop bop, const IR::U1& comparison, const IR::U1& bop_pred) {
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switch (bop) {
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case Bop::AND:
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return ir.LogicalAnd(comparison, bop_pred);
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case Bop::OR:
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return ir.LogicalOr(comparison, bop_pred);
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case Bop::XOR:
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return ir.LogicalXor(comparison, bop_pred);
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}
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throw NotImplementedException("Invalid ISETP bop {}", bop);
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}
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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union {
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union {
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u64 raw;
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u64 raw;
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@ -68,17 +17,18 @@ void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<45, 2, Bop> bop;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, CompareOp> compare_op;
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BitField<49, 3, CompareOp> compare_op;
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} const isetp{insn};
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} const isetp{insn};
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const Bop bop{isetp.bop};
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const BooleanOp bop{isetp.bop};
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const CompareOp compare_op{isetp.compare_op};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U1 comparison{Compare(v.ir, isetp.compare_op, op_a, op_b, isetp.is_signed != 0)};
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const IR::U1 comparison{IntegerCompare(v.ir, op_a, op_b, compare_op, isetp.is_signed != 0)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 result_a{Combine(v.ir, bop, comparison, bop_pred)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_b{Combine(v.ir, bop, v.ir.LogicalNot(comparison), bop_pred)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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v.ir.SetPred(isetp.dest_pred_a, result_a);
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v.ir.SetPred(isetp.dest_pred_a, result_a);
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v.ir.SetPred(isetp.dest_pred_b, result_b);
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v.ir.SetPred(isetp.dest_pred_b, result_b);
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}
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}
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@ -593,10 +593,6 @@ void TranslatorVisitor::PRMT_imm(u64) {
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ThrowNotImplemented(Opcode::PRMT_imm);
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ThrowNotImplemented(Opcode::PRMT_imm);
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}
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}
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void TranslatorVisitor::PSET(u64) {
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ThrowNotImplemented(Opcode::PSET);
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}
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void TranslatorVisitor::PSETP(u64) {
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void TranslatorVisitor::PSETP(u64) {
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ThrowNotImplemented(Opcode::PSETP);
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ThrowNotImplemented(Opcode::PSETP);
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}
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}
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@ -0,0 +1,41 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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void TranslatorVisitor::PSET(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<12, 3, IR::Pred> pred_a;
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BitField<15, 1, u64> neg_pred_a;
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BitField<24, 2, BooleanOp> bop_1;
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BitField<29, 3, IR::Pred> pred_b;
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BitField<32, 1, u64> neg_pred_b;
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BitField<39, 3, IR::Pred> pred_c;
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BitField<42, 1, u64> neg_pred_c;
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BitField<44, 1, u64> bf;
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BitField<45, 2, BooleanOp> bop_2;
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} const pset{insn};
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const IR::U1 pred_a{ir.GetPred(pset.pred_a, pset.neg_pred_a != 0)};
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const IR::U1 pred_b{ir.GetPred(pset.pred_b, pset.neg_pred_b != 0)};
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const IR::U1 pred_c{ir.GetPred(pset.pred_c, pset.neg_pred_c != 0)};
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const IR::U1 res_1{PredicateCombine(ir, pred_a, pred_b, pset.bop_1)};
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const IR::U1 res_2{PredicateCombine(ir, res_1, pred_c, pset.bop_2)};
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const IR::U32 true_result{pset.bf != 0 ? ir.Imm32(0x3f800000) : ir.Imm32(-1)};
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const IR::U32 false_result{ir.Imm32(0)};
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const IR::U32 result{ir.Select(res_2, true_result, false_result)};
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X(pset.dest_reg, result);
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}
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} // namespace Shader::Maxwell
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