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Merge pull request #532 from bunnei/ld_c
gl_shader_decompiler: Implement LD_C instruction.
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commit
cfc9effa6c
@ -109,11 +109,6 @@ union Sampler {
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u64 value{};
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};
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union Uniform {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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};
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} // namespace Shader
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} // namespace Tegra
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@ -180,6 +175,15 @@ enum class FloatRoundingOp : u64 {
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Trunc = 3,
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};
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enum class UniformType : u64 {
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UnsignedByte = 0,
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SignedByte = 1,
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UnsignedShort = 2,
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SignedShort = 3,
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Single = 4,
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Double = 5,
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};
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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value = instr.value;
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@ -257,6 +261,11 @@ union Instruction {
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BitField<49, 1, u64> negate_c;
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} ffma;
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union {
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BitField<48, 3, UniformType> type;
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BitField<44, 2, u64> unknown;
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} ld_c;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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@ -354,12 +363,21 @@ union Instruction {
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}
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} bra;
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union {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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} cbuf34;
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union {
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BitField<20, 16, s64> offset;
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BitField<36, 5, u64> index;
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} cbuf36;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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Attribute attribute;
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Uniform uniform;
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Sampler sampler;
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u64 value;
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@ -374,6 +392,7 @@ public:
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KIL,
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BRA,
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LD_A,
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LD_C,
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ST_A,
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TEX,
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TEXQ, // Texture Query
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@ -548,6 +567,7 @@ private:
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"),
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INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"),
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@ -654,7 +654,16 @@ u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, GLuint progr
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buffer_draw_state.bindpoint = current_bindpoint + bindpoint;
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boost::optional<VAddr> addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
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std::vector<u8> data(used_buffer.GetSize() * sizeof(float));
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std::vector<u8> data;
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if (used_buffer.IsIndirect()) {
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// Buffer is accessed indirectly, so upload the entire thing
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data.resize(buffer.size * sizeof(float));
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} else {
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// Buffer is accessed directly, upload just what we use
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data.resize(used_buffer.GetSize() * sizeof(float));
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}
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Memory::ReadBlock(*addr, data.data(), data.size());
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glBindBuffer(GL_SHADER_STORAGE_BUFFER, buffer_draw_state.ssbo);
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@ -20,7 +20,6 @@ using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Sampler;
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using Tegra::Shader::SubOp;
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using Tegra::Shader::Uniform;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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@ -365,11 +364,9 @@ public:
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}
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/// Generates code representing a uniform (C buffer) register, interpreted as the input type.
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std::string GetUniform(const Uniform& uniform, GLSLRegister::Type type) {
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declr_const_buffers[uniform.index].MarkAsUsed(static_cast<unsigned>(uniform.index),
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static_cast<unsigned>(uniform.offset), stage);
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std::string value =
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'c' + std::to_string(uniform.index) + '[' + std::to_string(uniform.offset) + ']';
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std::string GetUniform(u64 index, u64 offset, GLSLRegister::Type type) {
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declr_const_buffers[index].MarkAsUsed(index, offset, stage);
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std::string value = 'c' + std::to_string(index) + '[' + std::to_string(offset) + ']';
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if (type == GLSLRegister::Type::Float) {
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return value;
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@ -380,10 +377,19 @@ public:
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}
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}
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/// Generates code representing a uniform (C buffer) register, interpreted as the type of the
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/// destination register.
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std::string GetUniform(const Uniform& uniform, const Register& dest_reg) {
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return GetUniform(uniform, regs[dest_reg].GetActiveType());
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std::string GetUniformIndirect(u64 index, s64 offset, const Register& index_reg,
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GLSLRegister::Type type) {
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declr_const_buffers[index].MarkAsUsedIndirect(index, stage);
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std::string value = 'c' + std::to_string(index) + "[(floatBitsToInt(" +
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GetRegister(index_reg, 0) + ") + " + std::to_string(offset) + ") / 4]";
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if (type == GLSLRegister::Type::Float) {
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return value;
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} else if (type == GLSLRegister::Type::Integer) {
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return "floatBitsToInt(" + value + ')';
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} else {
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UNREACHABLE();
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}
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}
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/// Add declarations for registers
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@ -747,7 +753,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsFloat(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Float);
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}
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}
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@ -904,7 +911,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Integer);
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}
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}
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@ -936,7 +944,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Integer);
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}
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}
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@ -953,7 +962,8 @@ private:
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switch (opcode->GetId()) {
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case OpCode::Id::FFMA_CR: {
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Float);
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op_c += regs.GetRegisterAsFloat(instr.gpr39);
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break;
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}
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@ -964,7 +974,8 @@ private:
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}
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case OpCode::Id::FFMA_RC: {
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op_b += regs.GetRegisterAsFloat(instr.gpr39);
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op_c += regs.GetUniform(instr.uniform, instr.gpr0);
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op_c += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Float);
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break;
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}
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case OpCode::Id::FFMA_IMM: {
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@ -1079,6 +1090,33 @@ private:
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attribute);
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break;
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}
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case OpCode::Id::LD_C: {
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ASSERT_MSG(instr.ld_c.unknown == 0, "Unimplemented");
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std::string op_a =
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, instr.gpr8,
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GLSLRegister::Type::Float);
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std::string op_b =
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, instr.gpr8,
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GLSLRegister::Type::Float);
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switch (instr.ld_c.type.Value()) {
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case Tegra::Shader::UniformType::Single:
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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break;
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case Tegra::Shader::UniformType::Double:
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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regs.SetRegisterToFloat(instr.gpr0.Value() + 1, 0, op_b, 1, 1);
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break;
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled type: {}",
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static_cast<unsigned>(instr.ld_c.type.Value()));
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UNREACHABLE();
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}
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break;
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}
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case OpCode::Id::ST_A: {
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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regs.SetOutputAttributeToRegister(attribute, instr.attribute.fmt20.element,
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@ -1175,7 +1213,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsFloat(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Float);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Float);
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}
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}
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@ -1216,7 +1255,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20, 0, instr.isetp.is_signed);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Integer);
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}
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using Tegra::Shader::Pred;
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@ -1262,7 +1302,8 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsFloat(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Float);
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op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::Float);
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}
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}
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@ -22,17 +22,28 @@ class ConstBufferEntry {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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public:
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void MarkAsUsed(unsigned index, unsigned offset, Maxwell::ShaderStage stage) {
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void MarkAsUsed(u64 index, u64 offset, Maxwell::ShaderStage stage) {
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is_used = true;
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this->index = index;
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this->index = static_cast<unsigned>(index);
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this->stage = stage;
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max_offset = std::max(max_offset, static_cast<unsigned>(offset));
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}
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void MarkAsUsedIndirect(u64 index, Maxwell::ShaderStage stage) {
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is_used = true;
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is_indirect = true;
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this->index = static_cast<unsigned>(index);
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this->stage = stage;
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max_offset = std::max(max_offset, offset);
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}
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bool IsUsed() const {
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return is_used;
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}
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bool IsIndirect() const {
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return is_indirect;
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}
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unsigned GetIndex() const {
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return index;
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}
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@ -51,6 +62,7 @@ private:
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};
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bool is_used{};
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bool is_indirect{};
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unsigned index{};
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unsigned max_offset{};
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Maxwell::ShaderStage stage;
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