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dyncom: const correctness changes
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@ -51,7 +51,7 @@ enum {
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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static bool CondPassed(ARMul_State* cpu, unsigned int cond) {
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static bool CondPassed(const ARMul_State* cpu, unsigned int cond) {
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const bool n_flag = cpu->NFlag != 0;
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const bool z_flag = cpu->ZFlag != 0;
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const bool c_flag = cpu->CFlag != 0;
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@ -30,7 +30,7 @@
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* @return If the PC is being read, then the word-aligned PC value is returned.
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* If the PC is not being read, then the value stored in the register is returned.
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*/
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static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
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static inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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}
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@ -43,6 +43,6 @@ static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
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* @return If the PC is being read, then the incremented PC value is returned.
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* If the PC is not being read, then the values stored in the register is returned.
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*/
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static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) {
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static inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) {
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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}
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@ -249,7 +249,7 @@ enum : u32 {
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VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
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};
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static inline int vfp_single_type(vfp_single* s)
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static inline int vfp_single_type(const vfp_single* s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 255) {
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@ -293,7 +293,7 @@ static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
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// Re-pack a single-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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static inline s32 vfp_single_pack(vfp_single* s)
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static inline s32 vfp_single_pack(const vfp_single* s)
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{
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u32 val = (s->sign << 16) +
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(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
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@ -335,7 +335,7 @@ struct vfp_double {
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#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
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#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
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static inline int vfp_double_type(vfp_double* s)
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static inline int vfp_double_type(const vfp_double* s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 2047) {
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@ -379,7 +379,7 @@ static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
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// Re-pack a double-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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static inline s64 vfp_double_pack(vfp_double* s)
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static inline s64 vfp_double_pack(const vfp_double* s)
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{
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u64 val = ((u64)s->sign << 48) +
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((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
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