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gl_shader_decompiler: Implement non-immediate HADD2 and HMUL2 instructions
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@ -573,6 +573,22 @@ union Instruction {
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BitField<49, 1, u64> negate_a;
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} alu_integer;
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union {
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BitField<39, 1, u64> ftz;
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BitField<32, 1, u64> saturate;
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BitField<49, 2, HalfMerge> merge;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<47, 2, HalfType> type_b;
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BitField<35, 2, HalfType> type_c;
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} alu_half;
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union {
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BitField<40, 1, u64> invert;
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} popc;
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@ -1165,6 +1181,10 @@ public:
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LEA_RZ,
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LEA_IMM,
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LEA_HI,
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HADD2_C,
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HADD2_R,
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HMUL2_C,
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HMUL2_R,
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POPC_C,
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POPC_R,
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POPC_IMM,
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@ -1238,6 +1258,7 @@ public:
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ArithmeticImmediate,
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ArithmeticInteger,
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ArithmeticIntegerImmediate,
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ArithmeticHalf,
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Bfe,
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Shift,
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Ffma,
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@ -1409,6 +1430,10 @@ private:
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INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"),
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INST("010010111101----", Id::LEA_RZ, Type::ArithmeticInteger, "LEA_RZ"),
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INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"),
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INST("0111101-1-------", Id::HADD2_C, Type::ArithmeticHalf, "HADD2_C"),
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INST("0101110100010---", Id::HADD2_R, Type::ArithmeticHalf, "HADD2_R"),
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INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"),
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INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -1827,6 +1827,56 @@ private:
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break;
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}
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case OpCode::Type::ArithmeticHalf: {
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if (opcode->GetId() == OpCode::Id::HADD2_C || opcode->GetId() == OpCode::Id::HADD2_R) {
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ASSERT_MSG(instr.alu_half.ftz == 0, "Unimplemented");
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}
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const bool negate_a =
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opcode->GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
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const bool negate_b =
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opcode->GetId() != OpCode::Id::HMUL2_C && instr.alu_half.negate_b != 0;
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const std::string op_a =
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GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.alu_half.type_a,
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instr.alu_half.abs_a != 0, negate_a);
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std::string op_b;
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switch (opcode->GetId()) {
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HMUL2_C:
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op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::UnsignedInteger);
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break;
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case OpCode::Id::HADD2_R:
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case OpCode::Id::HMUL2_R:
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op_b = regs.GetRegisterAsInteger(instr.gpr20, 0, false);
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break;
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default:
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UNREACHABLE();
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op_b = "0";
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break;
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}
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op_b = GetHalfFloat(op_b, instr.alu_half.type_b, instr.alu_half.abs_b != 0, negate_b);
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const std::string result = [&]() {
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switch (opcode->GetId()) {
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HADD2_R:
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return '(' + op_a + " + " + op_b + ')';
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case OpCode::Id::HMUL2_C:
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case OpCode::Id::HMUL2_R:
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return '(' + op_a + " * " + op_b + ')';
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled half float instruction: {}", opcode->GetName());
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UNREACHABLE();
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return std::string("0");
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}
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}();
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regs.SetRegisterToHalfFloat(instr.gpr0, 0, result, instr.alu_half.merge, 1, 1,
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instr.alu_half.saturate != 0);
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break;
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}
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case OpCode::Type::Ffma: {
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const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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