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decode/register_set_predicate: Use move for shared pointers
Avoid atomic counters used by shared pointers.
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c5bf693882
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@ -2,6 +2,8 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <utility>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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@ -10,6 +12,7 @@
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namespace VideoCommon::Shader {
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using std::move;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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@ -23,7 +26,7 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF(instr.p2r_r2p.mode != Tegra::Shader::R2pMode::Pr);
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const Node apply_mask = [&] {
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Node apply_mask = [this, opcode, instr] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM:
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case OpCode::Id::P2R_IMM:
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@ -34,25 +37,23 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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}
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}();
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const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
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const u32 offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM: {
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const Node mask = GetRegister(instr.gpr8);
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Node mask = GetRegister(instr.gpr8);
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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const auto shift = static_cast<u32>(pred);
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const u32 shift = static_cast<u32>(pred);
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const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
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const Node condition =
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Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
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Node apply = BitfieldExtract(apply_mask, shift, 1);
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Node condition = Operation(OperationCode::LogicalUNotEqual, apply, Immediate(0));
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const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
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const Node value =
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Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
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Node compare = BitfieldExtract(mask, offset + shift, 1);
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Node value = Operation(OperationCode::LogicalUNotEqual, move(compare), Immediate(0));
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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bb.push_back(Conditional(condition, {code}));
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Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), move(value));
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bb.push_back(Conditional(condition, {move(code)}));
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}
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break;
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}
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@ -61,12 +62,12 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred),
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Immediate(0));
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value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit));
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value = Operation(OperationCode::UBitwiseOr, move(value), move(bit));
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}
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask);
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value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8);
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value = Operation(OperationCode::UBitwiseAnd, move(value), apply_mask);
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value = BitfieldInsert(GetRegister(instr.gpr8), move(value), offset, 8);
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SetRegister(bb, instr.gpr0, std::move(value));
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SetRegister(bb, instr.gpr0, move(value));
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break;
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}
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default:
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