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Merge pull request #9415 from liamwhite/dc
memory: correct semantics of data cache management operations
This commit is contained in:
commit
d5684dbe7d
@ -34,8 +34,6 @@ add_library(common STATIC
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bit_util.h
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bit_util.h
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cityhash.cpp
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cityhash.cpp
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cityhash.h
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cityhash.h
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cache_management.cpp
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cache_management.h
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common_funcs.h
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common_funcs.h
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common_precompiled_headers.h
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common_precompiled_headers.h
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common_types.h
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common_types.h
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@ -1,59 +0,0 @@
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// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cstdint>
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#include <cstring>
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#include "common/cache_management.h"
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namespace Common {
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#if defined(ARCHITECTURE_x86_64)
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// Most cache operations are no-ops on x86
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void DataCacheLineCleanByVAToPoU(void* start, size_t size) {}
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void DataCacheLineCleanAndInvalidateByVAToPoC(void* start, size_t size) {}
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void DataCacheLineCleanByVAToPoC(void* start, size_t size) {}
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void DataCacheZeroByVA(void* start, size_t size) {
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std::memset(start, 0, size);
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}
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#elif defined(ARCHITECTURE_arm64)
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// BS/DminLine is log2(cache size in words), we want size in bytes
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#define EXTRACT_DMINLINE(ctr_el0) (1 << ((((ctr_el0) >> 16) & 0xf) + 2))
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#define EXTRACT_BS(dczid_el0) (1 << (((dczid_el0)&0xf) + 2))
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#define DEFINE_DC_OP(op_name, function_name) \
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void function_name(void* start, size_t size) { \
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size_t ctr_el0; \
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asm volatile("mrs %[ctr_el0], ctr_el0\n\t" : [ctr_el0] "=r"(ctr_el0)); \
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size_t cacheline_size = EXTRACT_DMINLINE(ctr_el0); \
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uintptr_t va_start = reinterpret_cast<uintptr_t>(start); \
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uintptr_t va_end = va_start + size; \
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for (uintptr_t va = va_start; va < va_end; va += cacheline_size) { \
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asm volatile("dc " #op_name ", %[va]\n\t" : : [va] "r"(va) : "memory"); \
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} \
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}
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#define DEFINE_DC_OP_DCZID(op_name, function_name) \
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void function_name(void* start, size_t size) { \
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size_t dczid_el0; \
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asm volatile("mrs %[dczid_el0], dczid_el0\n\t" : [dczid_el0] "=r"(dczid_el0)); \
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size_t cacheline_size = EXTRACT_BS(dczid_el0); \
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uintptr_t va_start = reinterpret_cast<uintptr_t>(start); \
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uintptr_t va_end = va_start + size; \
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for (uintptr_t va = va_start; va < va_end; va += cacheline_size) { \
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asm volatile("dc " #op_name ", %[va]\n\t" : : [va] "r"(va) : "memory"); \
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} \
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}
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DEFINE_DC_OP(cvau, DataCacheLineCleanByVAToPoU);
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DEFINE_DC_OP(civac, DataCacheLineCleanAndInvalidateByVAToPoC);
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DEFINE_DC_OP(cvac, DataCacheLineCleanByVAToPoC);
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DEFINE_DC_OP_DCZID(zva, DataCacheZeroByVA);
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#endif
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} // namespace Common
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@ -1,27 +0,0 @@
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// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <cstddef>
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namespace Common {
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// Data cache instructions enabled at EL0 by SCTLR_EL1.UCI.
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// VA = virtual address
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// PoC = point of coherency
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// PoU = point of unification
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// dc cvau
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void DataCacheLineCleanByVAToPoU(void* start, size_t size);
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// dc civac
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void DataCacheLineCleanAndInvalidateByVAToPoC(void* start, size_t size);
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// dc cvac
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void DataCacheLineCleanByVAToPoC(void* start, size_t size);
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// dc zva
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void DataCacheZeroByVA(void* start, size_t size);
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} // namespace Common
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@ -6,7 +6,6 @@
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/atomic_ops.h"
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#include "common/atomic_ops.h"
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#include "common/cache_management.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "common/page_table.h"
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#include "common/page_table.h"
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@ -340,10 +339,9 @@ struct Memory::Impl {
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LOG_ERROR(HW_Memory, "Unmapped cache maintenance @ {:#018X}", current_vaddr);
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LOG_ERROR(HW_Memory, "Unmapped cache maintenance @ {:#018X}", current_vaddr);
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throw InvalidMemoryException();
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throw InvalidMemoryException();
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},
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},
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[&](const std::size_t block_size, u8* const host_ptr) { cb(block_size, host_ptr); },
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[&](const std::size_t block_size, u8* const host_ptr) {},
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[&](const VAddr current_vaddr, const std::size_t block_size, u8* const host_ptr) {
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[&](const VAddr current_vaddr, const std::size_t block_size, u8* const host_ptr) {
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system.GPU().FlushRegion(current_vaddr, block_size);
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cb(current_vaddr, block_size);
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cb(block_size, host_ptr);
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},
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},
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[](const std::size_t block_size) {});
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[](const std::size_t block_size) {});
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} catch (InvalidMemoryException&) {
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} catch (InvalidMemoryException&) {
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@ -354,27 +352,30 @@ struct Memory::Impl {
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}
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}
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Result InvalidateDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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Result InvalidateDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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auto on_rasterizer = [&](const VAddr current_vaddr, const std::size_t block_size) {
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// Do nothing; this operation (dc ivac) cannot be supported
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// dc ivac: Invalidate to point of coherency
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// from EL0
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// GPU flush -> CPU invalidate
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system.GPU().FlushRegion(current_vaddr, block_size);
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};
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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return PerformCacheOperation(process, dest_addr, size, on_rasterizer);
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}
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}
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Result StoreDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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Result StoreDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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auto on_rasterizer = [&](const VAddr current_vaddr, const std::size_t block_size) {
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// dc cvac: Store to point of coherency
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// dc cvac: Store to point of coherency
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Common::DataCacheLineCleanByVAToPoC(host_ptr, block_size);
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// CPU flush -> GPU invalidate
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system.GPU().InvalidateRegion(current_vaddr, block_size);
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};
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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return PerformCacheOperation(process, dest_addr, size, on_rasterizer);
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}
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}
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Result FlushDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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Result FlushDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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auto on_rasterizer = [&](const VAddr current_vaddr, const std::size_t block_size) {
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// dc civac: Store to point of coherency, and invalidate from cache
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// dc civac: Store to point of coherency, and invalidate from cache
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Common::DataCacheLineCleanAndInvalidateByVAToPoC(host_ptr, block_size);
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// CPU flush -> GPU invalidate
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system.GPU().InvalidateRegion(current_vaddr, block_size);
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};
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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return PerformCacheOperation(process, dest_addr, size, on_rasterizer);
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}
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}
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void MarkRegionDebug(VAddr vaddr, u64 size, bool debug) {
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void MarkRegionDebug(VAddr vaddr, u64 size, bool debug) {
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