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Merge pull request #2299 from lioncash/maxwell
gl_shader_manager: Remove reliance on a global accessor within MaxwellUniformData::SetFromRegs()
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commit
d7438d067f
@ -318,7 +318,7 @@ void RasterizerOpenGL::SetupShaders(GLenum primitive_mode) {
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const std::size_t stage{index == 0 ? 0 : index - 1}; // Stage indices are 0 - 5
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GLShader::MaxwellUniformData ubo{};
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ubo.SetFromRegs(gpu.state.shader_stages[stage]);
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ubo.SetFromRegs(gpu, stage);
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const GLintptr offset = buffer_cache.UploadHostMemory(
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&ubo, sizeof(ubo), static_cast<std::size_t>(uniform_buffer_alignment));
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@ -6,13 +6,11 @@
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#include "common/assert.h"
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#include "common/hash.h"
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#include "core/core.h"
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#include "core/memory.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/renderer_opengl/gl_rasterizer.h"
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#include "video_core/renderer_opengl/gl_shader_cache.h"
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#include "video_core/renderer_opengl/gl_shader_decompiler.h"
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#include "video_core/renderer_opengl/gl_shader_disk_cache.h"
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#include "video_core/renderer_opengl/gl_shader_manager.h"
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#include "video_core/renderer_opengl/utils.h"
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#include "video_core/shader/shader_ir.h"
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@ -2,15 +2,15 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/core.h"
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#include "video_core/renderer_opengl/gl_shader_manager.h"
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namespace OpenGL::GLShader {
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void MaxwellUniformData::SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage) {
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const auto& gpu = Core::System::GetInstance().GPU().Maxwell3D();
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const auto& regs = gpu.regs;
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const auto& state = gpu.state;
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using Tegra::Engines::Maxwell3D;
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void MaxwellUniformData::SetFromRegs(const Maxwell3D& maxwell, std::size_t shader_stage) {
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const auto& regs = maxwell.regs;
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const auto& state = maxwell.state;
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// TODO(bunnei): Support more than one viewport
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viewport_flip[0] = regs.viewport_transform[0].scale_x < 0.0 ? -1.0f : 1.0f;
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@ -18,7 +18,7 @@ void MaxwellUniformData::SetFromRegs(const Maxwell3D::State::ShaderStageInfo& sh
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u32 func = static_cast<u32>(regs.alpha_test_func);
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// Normalize the gl variants of opCompare to be the same as the normal variants
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u32 op_gl_variant_base = static_cast<u32>(Tegra::Engines::Maxwell3D::Regs::ComparisonOp::Never);
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const u32 op_gl_variant_base = static_cast<u32>(Maxwell3D::Regs::ComparisonOp::Never);
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if (func >= op_gl_variant_base) {
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func = func - op_gl_variant_base + 1U;
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}
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@ -31,8 +31,9 @@ void MaxwellUniformData::SetFromRegs(const Maxwell3D::State::ShaderStageInfo& sh
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// Assign in which stage the position has to be flipped
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// (the last stage before the fragment shader).
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if (gpu.regs.shader_config[static_cast<u32>(Maxwell3D::Regs::ShaderProgram::Geometry)].enable) {
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flip_stage = static_cast<u32>(Maxwell3D::Regs::ShaderProgram::Geometry);
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constexpr u32 geometry_index = static_cast<u32>(Maxwell3D::Regs::ShaderProgram::Geometry);
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if (maxwell.regs.shader_config[geometry_index].enable) {
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flip_stage = geometry_index;
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} else {
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flip_stage = static_cast<u32>(Maxwell3D::Regs::ShaderProgram::VertexB);
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}
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@ -12,14 +12,13 @@
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namespace OpenGL::GLShader {
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using Tegra::Engines::Maxwell3D;
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/// Uniform structure for the Uniform Buffer Object, all vectors must be 16-byte aligned
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// NOTE: Always keep a vec4 at the end. The GL spec is not clear whether the alignment at
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// the end of a uniform block is included in UNIFORM_BLOCK_DATA_SIZE or not.
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// Not following that rule will cause problems on some AMD drivers.
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/// @note Always keep a vec4 at the end. The GL spec is not clear whether the alignment at
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/// the end of a uniform block is included in UNIFORM_BLOCK_DATA_SIZE or not.
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/// Not following that rule will cause problems on some AMD drivers.
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struct MaxwellUniformData {
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void SetFromRegs(const Maxwell3D::State::ShaderStageInfo& shader_stage);
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void SetFromRegs(const Tegra::Engines::Maxwell3D& maxwell, std::size_t shader_stage);
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alignas(16) GLvec4 viewport_flip;
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struct alignas(16) {
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GLuint instance_id;
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