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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-22 08:53:22 +02:00
commit
dd21f986b8
@ -871,6 +871,8 @@ typedef struct _mvn_inst {
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typedef struct _rev_inst {
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unsigned int Rd;
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unsigned int Rm;
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unsigned int op1;
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unsigned int op2;
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} rev_inst;
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typedef struct _rsb_inst {
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@ -2093,36 +2095,33 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
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rev_inst *inst_cream = (rev_inst *)inst_base->component;
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
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rev_inst* const inst_cream = (rev_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 22);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index){
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
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rev_inst *inst_cream = (rev_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 12, 15);
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return inst_base;
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(rev)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("REVSH"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(rev)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index)
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{
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@ -5090,39 +5089,40 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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QDADD_INST:
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QDSUB_INST:
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QSUB_INST:
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REV_INST:
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REV16_INST:
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REVSH_INST:
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{
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rev_inst *inst_cream = (rev_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = ((RM & 0xff) << 24) |
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(((RM >> 8) & 0xff) << 16) |
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(((RM >> 16) & 0xff) << 8) |
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((RM >> 24) & 0xff);
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if (inst_cream->Rm == 15) {
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LOG_ERROR(Core_ARM11, "invalid operand for REV");
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CITRA_IGNORE_EXIT(-1);
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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rev_inst* const inst_cream = (rev_inst*)inst_base->component;
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const u8 op1 = inst_cream->op1;
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const u8 op2 = inst_cream->op2;
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// REV
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if (op1 == 0x03 && op2 == 0x01) {
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RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) | ((RM >> 24) & 0xFF);
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}
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// REV16
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else if (op1 == 0x03 && op2 == 0x05) {
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RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) | ((RM & 0xFF000000) >> 8);
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}
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// REVSH
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else if (op1 == 0x07 && op2 == 0x05) {
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RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8);
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if (RD & 0x8000)
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RD |= 0xffff0000;
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(rev_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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REV16_INST:
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{
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rev_inst *inst_cream = (rev_inst *)inst_base->component;
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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RD = (BITS(RM, 0, 7) << 8) |
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BITS(RM, 8, 15) |
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(BITS(RM, 16, 23) << 24) |
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(BITS(RM, 24, 31) << 16);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(rev_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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REVSH_INST:
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RFE_INST:
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RSB_INST:
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{
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