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shader_decode: Implement HFMA2
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@ -648,6 +648,7 @@ union Instruction {
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BitField<37, 2, HalfPrecision> precision;
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BitField<32, 1, u64> saturate;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> negate_c;
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BitField<35, 2, HalfType> type_c;
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} rr;
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@ -2,6 +2,8 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <tuple>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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@ -9,6 +11,8 @@
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namespace VideoCommon::Shader {
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using Tegra::Shader::HalfPrecision;
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using Tegra::Shader::HalfType;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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@ -16,7 +20,55 @@ u32 ShaderIR::DecodeHfma2(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED();
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if (opcode->get().GetId() == OpCode::Id::HFMA2_RR) {
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UNIMPLEMENTED_IF(instr.hfma2.rr.precision != HalfPrecision::None);
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} else {
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UNIMPLEMENTED_IF(instr.hfma2.precision != HalfPrecision::None);
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}
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constexpr auto identity = HalfType::H0_H1;
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const HalfType type_a = instr.hfma2.type_a;
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const Node op_a = GetRegister(instr.gpr8);
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bool neg_b{}, neg_c{};
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auto [saturate, type_b, op_b, type_c,
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op_c] = [&]() -> std::tuple<bool, HalfType, Node, HalfType, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::HFMA2_CR:
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_b,
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), instr.hfma2.type_reg39,
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GetRegister(instr.gpr39)};
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case OpCode::Id::HFMA2_RC:
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_reg39, GetRegister(instr.gpr39),
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instr.hfma2.type_b, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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case OpCode::Id::HFMA2_RR:
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neg_b = instr.hfma2.rr.negate_b;
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neg_c = instr.hfma2.rr.negate_c;
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return {instr.hfma2.rr.saturate, instr.hfma2.type_b, GetRegister(instr.gpr20),
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instr.hfma2.rr.type_c, GetRegister(instr.gpr39)};
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case OpCode::Id::HFMA2_IMM_R:
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, identity, UnpackHalfImmediate(instr, true),
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instr.hfma2.type_reg39, GetRegister(instr.gpr39)};
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default:
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return {false, identity, Immediate(0), identity, Immediate(0)};
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}
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}();
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UNIMPLEMENTED_IF_MSG(saturate, "HFMA2 saturation is not implemented");
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op_b = GetOperandAbsNegHalf(op_b, false, neg_b);
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op_c = GetOperandAbsNegHalf(op_c, false, neg_c);
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MetaHalfArithmetic meta{true, {type_a, type_b, type_c}};
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Node value = Operation(OperationCode::HFma, meta, op_a, op_b, op_c);
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.hfma2.merge);
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SetRegister(bb, instr.gpr0, value);
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return pc;
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}
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@ -762,9 +762,9 @@ private:
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return GenerateBinaryInfix(operation, "/", type, type, type);
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}
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std::string FFma(Operation operation) {
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return GenerateTernary(operation, "fma", Type::Float, Type::Float, Type::Float,
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Type::Float);
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template <Type type>
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std::string Fma(Operation operation) {
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return GenerateTernary(operation, "fma", type, type, type, type);
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}
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template <Type type>
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@ -1231,7 +1231,7 @@ private:
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&Add<Type::Float>,
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&Mul<Type::Float>,
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&Div<Type::Float>,
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&FFma,
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&Fma<Type::Float>,
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&Negate<Type::Float>,
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&Absolute<Type::Float>,
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&FClamp,
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@ -1289,6 +1289,7 @@ private:
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&Add<Type::HalfFloat>,
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&Mul<Type::HalfFloat>,
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&Fma<Type::HalfFloat>,
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&Absolute<Type::HalfFloat>,
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&HNegate,
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&HMergeF32,
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@ -110,6 +110,7 @@ enum class OperationCode {
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HAdd, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HFma, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b, f16vec2 c) -> f16vec2
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HAbsolute, /// (f16vec2 a) -> f16vec2
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HNegate, /// (f16vec2 a, bool first, bool second) -> f16vec2
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HMergeF32, /// (f16vec2 src) -> float
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