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dyncom: Fix SMULWB/SMULWT
Wasn't doing proper sign-extension
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parent
317fe1e528
commit
df5e0f9f28
@ -5891,16 +5891,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMULW_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
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int64_t rm = RM;
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int64_t rn = RN;
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if (inst_cream->m)
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rm = BITS(rm, 16, 31);
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else
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rm = BITS(rm, 0, 15);
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int64_t rst = rm * rn;
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RD = BITS(rst, 16, 47);
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF);
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s64 result = (s64)rm * (s64)(s32)RN;
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RD = BITS(result, 16, 47);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(smlad_inst));
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