diff --git a/src/shader_recompiler/backend/glsl/emit_glsl_image.cpp b/src/shader_recompiler/backend/glsl/emit_glsl_image.cpp index f335c8af04..418505475e 100644 --- a/src/shader_recompiler/backend/glsl/emit_glsl_image.cpp +++ b/src/shader_recompiler/backend/glsl/emit_glsl_image.cpp @@ -143,6 +143,21 @@ IR::Inst* PrepareSparse(IR::Inst& inst) { } return sparse_inst; } + +std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::string_view texture, + std::string_view coords) { + switch (info.type) { + case TextureType::Color2D: + case TextureType::Color2DRect: + return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture); + case TextureType::ColorArray2D: + case TextureType::ColorCube: + return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords, + texture); + default: + return std::string{coords}; + } +} } // Anonymous namespace void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, @@ -340,6 +355,13 @@ void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING"); ctx.AddU1("{}=true;", *sparse_inst); } + std::string coords_with_subpixel_offset; + if (ctx.profile.need_gather_subpixel_offset) { + // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on + // AMD hardware as on Maxwell or other Nvidia architectures. + coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords); + coords = coords_with_subpixel_offset; + } if (!sparse_inst || !supports_sparse) { if (offset.IsEmpty()) { ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords, @@ -387,6 +409,13 @@ void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& inde LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING"); ctx.AddU1("{}=true;", *sparse_inst); } + std::string coords_with_subpixel_offset; + if (ctx.profile.need_gather_subpixel_offset) { + // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on + // AMD hardware as on Maxwell or other Nvidia architectures. + coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords); + coords = coords_with_subpixel_offset; + } if (!sparse_inst || !supports_sparse) { if (offset.IsEmpty()) { ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref); diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp index 02073c420e..7d901c04b1 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp @@ -261,6 +261,30 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) { const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))}; return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value); } + +Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture, + Id coords) { + // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on + // AMD hardware as on Maxwell or other Nvidia architectures. + const auto calculate_coords{[&](size_t dim) { + const Id nudge{ctx.Const(0x1p-9f)}; + const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)}; + Id offset{dim == 2 ? ctx.ConstantComposite(ctx.F32[dim], nudge, nudge) + : ctx.ConstantComposite(ctx.F32[dim], nudge, nudge, ctx.f32_zero_value)}; + offset = ctx.OpFDiv(ctx.F32[dim], offset, ctx.OpConvertUToF(ctx.F32[dim], image_size)); + return ctx.OpFAdd(ctx.F32[dim], coords, offset); + }}; + switch (info.type) { + case TextureType::Color2D: + case TextureType::Color2DRect: + return calculate_coords(2); + case TextureType::ColorArray2D: + case TextureType::ColorCube: + return calculate_coords(3); + default: + return coords; + } +} } // Anonymous namespace Id EmitBindlessImageSampleImplicitLod(EmitContext&) { @@ -423,6 +447,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id const IR::Value& offset, const IR::Value& offset2) { const auto info{inst->Flags()}; const ImageOperands operands(ctx, offset, offset2); + if (ctx.profile.need_gather_subpixel_offset) { + coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords); + } return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst, ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component), operands.MaskOptional(), operands.Span()); @@ -432,6 +459,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, const IR::Value& offset, const IR::Value& offset2, Id dref) { const auto info{inst->Flags()}; const ImageOperands operands(ctx, offset, offset2); + if (ctx.profile.need_gather_subpixel_offset) { + coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords); + } return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst, ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(), operands.Span()); diff --git a/src/shader_recompiler/profile.h b/src/shader_recompiler/profile.h index 253e0d0bdd..9f88fb4407 100644 --- a/src/shader_recompiler/profile.h +++ b/src/shader_recompiler/profile.h @@ -52,6 +52,10 @@ struct Profile { bool need_declared_frag_colors{}; /// Prevents fast math optimizations that may cause inaccuracies bool need_fastmath_off{}; + /// Some GPU vendors use a different rounding precision when calculating texture pixel + /// coordinates with the 16.8 format in the ImageGather instruction than the Maxwell + /// architecture. Applying an offset does fix this mismatching rounding behaviour. + bool need_gather_subpixel_offset{}; /// OpFClamp is broken and OpFMax + OpFMin should be used instead bool has_broken_spirv_clamp{}; diff --git a/src/video_core/renderer_opengl/gl_device.h b/src/video_core/renderer_opengl/gl_device.h index 3ff8cad83b..cc0b95f1a5 100644 --- a/src/video_core/renderer_opengl/gl_device.h +++ b/src/video_core/renderer_opengl/gl_device.h @@ -176,6 +176,10 @@ public: return vendor_name == "ATI Technologies Inc."; } + bool IsIntel() const { + return vendor_name == "Intel"; + } + bool CanReportMemoryUsage() const { return can_report_memory; } diff --git a/src/video_core/renderer_opengl/gl_shader_cache.cpp b/src/video_core/renderer_opengl/gl_shader_cache.cpp index 479bb8ba3d..6ecda29842 100644 --- a/src/video_core/renderer_opengl/gl_shader_cache.cpp +++ b/src/video_core/renderer_opengl/gl_shader_cache.cpp @@ -218,6 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo .lower_left_origin_mode = true, .need_declared_frag_colors = true, .need_fastmath_off = device.NeedsFastmathOff(), + .need_gather_subpixel_offset = device.IsAmd() || device.IsIntel(), .has_broken_spirv_clamp = true, .has_broken_unsigned_image_offsets = true, diff --git a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp index 0684cceed3..985cc32034 100644 --- a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp +++ b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp @@ -329,6 +329,11 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device .lower_left_origin_mode = false, .need_declared_frag_colors = false, + .need_gather_subpixel_offset = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY || + driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE || + driver_id == VK_DRIVER_ID_MESA_RADV || + driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS || + driver_id == VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA, .has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS, .has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,