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dyncom: Implement SMLALD/SMLSLD
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031237e52c
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@ -972,6 +972,16 @@ typedef struct _smlal_inst {
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unsigned int RdLo;
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} smlal_inst;
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typedef struct smlald_inst {
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unsigned int RdLo;
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unsigned int RdHi;
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unsigned int Rm;
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unsigned int Rn;
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unsigned int swap;
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unsigned int op1;
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unsigned int op2;
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} smlald_inst;
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typedef struct _mla_inst {
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unsigned int S;
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unsigned int Rn;
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@ -2360,9 +2370,32 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLAW"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSLD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlald_inst));
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smlald_inst* const inst_cream = (smlald_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 8, 11);
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->RdLo = BITS(inst, 12, 15);
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inst_cream->RdHi = BITS(inst, 16, 19);
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inst_cream->swap = BIT(inst, 5);
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inst_cream->op1 = BITS(inst, 20, 22);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smlald)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index)
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{
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@ -5519,9 +5552,45 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SMLALXY_INST:
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SMLALD_INST:
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SMLAW_INST:
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SMLALD_INST:
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SMLSLD_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smlald_inst* const inst_cream = (smlald_inst*)inst_base->component;
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const bool do_swap = (inst_cream->swap == 1);
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const u32 rdlo_val = RDLO;
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const u32 rdhi_val = RDHI;
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const u32 rn_val = RN;
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u32 rm_val = RM;
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if (do_swap)
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rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16));
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const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF);
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const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF);
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s64 result;
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// SMLALD
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if (BIT(inst_cream->op2, 1) == 0) {
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result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32));
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}
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// SMLSLD
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else {
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result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32));
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}
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RDLO = (result & 0xFFFFFFFF);
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RDHI = ((result >> 32) & 0xFFFFFFFF);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(smlald_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMMLA_INST:
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SMMLS_INST:
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