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shader_decode: Implement FSET
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@ -16,7 +16,42 @@ u32 ShaderIR::DecodeFloatSet(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED();
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fset.abs_a != 0,
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instr.fset.neg_a != 0);
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Node op_b = [&]() {
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if (instr.is_b_imm) {
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return GetImmediate19(instr);
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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}
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}();
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op_b = GetOperandAbsNegFloat(op_b, instr.fset.abs_b != 0, instr.fset.neg_b != 0);
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// The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
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// condition is true, and to 0 otherwise.
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const Node second_pred = GetPredicate(instr.fset.pred39, instr.fset.neg_pred != 0);
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const OperationCode combiner = GetPredicateCombiner(instr.fset.op);
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const Node first_pred = GetPredicateComparisonFloat(instr.fset.cond, op_a, op_b);
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const Node predicate = Operation(combiner, first_pred, second_pred);
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const Node true_value = instr.fset.bf ? Immediate(1.0f) : Immediate(-1);
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const Node false_value = instr.fset.bf ? Immediate(0.0f) : Immediate(0);
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const Node value =
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Operation(OperationCode::Select, PRECISE, predicate, true_value, false_value);
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SetRegister(bb, instr.gpr0, value);
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if (instr.generates_cc.Value() != 0) {
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const Node is_zero = Operation(OperationCode::LogicalFEqual, predicate, Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, is_zero);
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LOG_WARNING(HW_GPU, "FSET condition code is incomplete");
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}
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return pc;
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}
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