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dyncom: Fix conditional execution of MSR
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parent
542b0b0057
commit
eabfa5cf43
@ -4964,39 +4964,41 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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MSR_INST:
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{
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msr_inst *inst_cream = (msr_inst *)inst_base->component;
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const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
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unsigned int inst = inst_cream->inst;
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unsigned int operand;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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msr_inst *inst_cream = (msr_inst *)inst_base->component;
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const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
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unsigned int inst = inst_cream->inst;
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unsigned int operand;
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if (BIT(inst, 25)) {
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int rot_imm = BITS(inst, 8, 11) * 2;
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operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm);
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} else {
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operand = cpu->Reg[BITS(inst, 0, 3)];
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}
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uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
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| (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
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uint32_t mask;
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if (!inst_cream->R) {
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if (InAPrivilegedMode(cpu)) {
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if ((operand & StateMask) != 0) {
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/// UNPREDICTABLE
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DEBUG_MSG;
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} else
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mask = byte_mask & (UserMask | PrivMask);
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if (BIT(inst, 25)) {
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int rot_imm = BITS(inst, 8, 11) * 2;
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operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm);
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} else {
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mask = byte_mask & UserMask;
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operand = cpu->Reg[BITS(inst, 0, 3)];
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}
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SAVE_NZCVT;
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uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
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| (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
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uint32_t mask;
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if (!inst_cream->R) {
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if (InAPrivilegedMode(cpu)) {
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if ((operand & StateMask) != 0) {
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/// UNPREDICTABLE
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DEBUG_MSG;
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} else
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mask = byte_mask & (UserMask | PrivMask);
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} else {
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mask = byte_mask & UserMask;
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}
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SAVE_NZCVT;
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cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask);
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switch_mode(cpu, cpu->Cpsr & 0x1f);
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LOAD_NZCVT;
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} else {
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if (CurrentModeHasSPSR) {
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mask = byte_mask & (UserMask | PrivMask | StateMask);
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cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask);
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cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask);
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switch_mode(cpu, cpu->Cpsr & 0x1f);
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LOAD_NZCVT;
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} else {
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if (CurrentModeHasSPSR) {
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mask = byte_mask & (UserMask | PrivMask | StateMask);
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cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask);
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}
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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