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Merge pull request #2074 from ReinUsesLisp/shader-ir-unify-offset
shader_ir: Unify constant buffer offset values
This commit is contained in:
commit
eceab45dac
@ -1248,11 +1248,19 @@ union Instruction {
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union {
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BitField<20, 14, u64> offset;
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BitField<34, 5, u64> index;
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u64 GetOffset() const {
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return offset * 4;
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}
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} cbuf34;
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union {
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BitField<20, 16, s64> offset;
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BitField<36, 5, u64> index;
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s64 GetOffset() const {
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return offset;
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}
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} cbuf36;
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// Unsure about the size of this one.
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@ -954,7 +954,7 @@ void RasterizerOpenGL::SetupConstBuffers(Tegra::Engines::Maxwell3D::Regs::Shader
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}
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} else {
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// Buffer is accessed directly, upload just what we use
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size = used_buffer.GetSize() * sizeof(float);
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size = used_buffer.GetSize();
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}
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// Align the actual size so it ends up being a multiple of vec4 to meet the OpenGL std140
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@ -543,8 +543,9 @@ private:
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if (const auto immediate = std::get_if<ImmediateNode>(offset)) {
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// Direct access
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const u32 offset_imm = immediate->GetValue();
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return fmt::format("{}[{}][{}]", GetConstBuffer(cbuf->GetIndex()), offset_imm / 4,
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offset_imm % 4);
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ASSERT_MSG(offset_imm % 4 == 0, "Unaligned cbuf direct access");
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return fmt::format("{}[{}][{}]", GetConstBuffer(cbuf->GetIndex()),
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offset_imm / (4 * 4), (offset_imm / 4) % 4);
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} else if (std::holds_alternative<OperationNode>(*offset)) {
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// Indirect access
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@ -25,7 +25,7 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -35,7 +35,7 @@ u32 ShaderIR::DecodeArithmeticHalf(BasicBlock& bb, const BasicBlock& code, u32 p
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switch (opcode->get().GetId()) {
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case OpCode::Id::HADD2_C:
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case OpCode::Id::HMUL2_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::HADD2_R:
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case OpCode::Id::HMUL2_R:
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return GetRegister(instr.gpr20);
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@ -26,7 +26,7 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, const BasicBlock& code, u3
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -48,7 +48,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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const bool input_signed = instr.conversion.is_input_signed;
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@ -72,7 +72,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -110,7 +110,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -27,14 +27,14 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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auto [op_b, op_c] = [&]() -> std::tuple<Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::FFMA_CR: {
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return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset()),
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GetRegister(instr.gpr39)};
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}
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case OpCode::Id::FFMA_RR:
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return {GetRegister(instr.gpr20), GetRegister(instr.gpr39)};
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case OpCode::Id::FFMA_RC: {
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return {GetRegister(instr.gpr39),
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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}
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case OpCode::Id::FFMA_IMM:
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return {GetImmediate19(instr), GetRegister(instr.gpr39)};
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@ -25,7 +25,7 @@ u32 ShaderIR::DecodeFloatSet(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -25,7 +25,7 @@ u32 ShaderIR::DecodeFloatSetPredicate(BasicBlock& bb, const BasicBlock& code, u3
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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op_b = GetOperandAbsNegFloat(op_b, instr.fsetp.abs_b, false);
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@ -39,13 +39,14 @@ u32 ShaderIR::DecodeHfma2(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_b,
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), instr.hfma2.type_reg39,
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GetRegister(instr.gpr39)};
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset()),
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instr.hfma2.type_reg39, GetRegister(instr.gpr39)};
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case OpCode::Id::HFMA2_RC:
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neg_b = instr.hfma2.negate_b;
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neg_c = instr.hfma2.negate_c;
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return {instr.hfma2.saturate, instr.hfma2.type_reg39, GetRegister(instr.gpr39),
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instr.hfma2.type_b, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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instr.hfma2.type_b,
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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case OpCode::Id::HFMA2_RR:
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neg_b = instr.hfma2.rr.negate_b;
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neg_c = instr.hfma2.rr.negate_c;
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@ -23,7 +23,7 @@ u32 ShaderIR::DecodeIntegerSet(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -25,7 +25,7 @@ u32 ShaderIR::DecodeIntegerSetPredicate(BasicBlock& bb, const BasicBlock& code,
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -80,7 +80,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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Node index = GetRegister(instr.gpr8);
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const Node op_a =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, index);
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
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switch (instr.ld_c.type.Value()) {
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case Tegra::Shader::UniformType::Single:
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@ -89,7 +89,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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case Tegra::Shader::UniformType::Double: {
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const Node op_b =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index);
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SetTemporal(bb, 0, op_a);
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SetTemporal(bb, 1, op_b);
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@ -142,7 +142,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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ASSERT(cbuf != nullptr);
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const auto cbuf_offset_imm = std::get_if<ImmediateNode>(cbuf->GetOffset());
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ASSERT(cbuf_offset_imm != nullptr);
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const auto cbuf_offset = cbuf_offset_imm->GetValue() * 4;
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const auto cbuf_offset = cbuf_offset_imm->GetValue();
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bb.push_back(Comment(
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fmt::format("Base address is c[0x{:x}][0x{:x}]", cbuf->GetIndex(), cbuf_offset)));
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@ -23,7 +23,7 @@ u32 ShaderIR::DecodeShift(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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@ -32,13 +32,14 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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auto [is_merge, op_b, op_c] = [&]() -> std::tuple<bool, Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::XMAD_CR:
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return {instr.xmad.merge_56, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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return {instr.xmad.merge_56,
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset()),
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GetRegister(instr.gpr39)};
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case OpCode::Id::XMAD_RR:
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return {instr.xmad.merge_37, GetRegister(instr.gpr20), GetRegister(instr.gpr39)};
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case OpCode::Id::XMAD_RC:
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return {false, GetRegister(instr.gpr39),
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset())};
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case OpCode::Id::XMAD_IMM:
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return {instr.xmad.merge_37, Immediate(static_cast<u32>(instr.xmad.imm20_16)),
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GetRegister(instr.gpr39)};
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@ -249,7 +249,7 @@ public:
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}
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u32 GetSize() const {
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return max_offset + 1;
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return max_offset + sizeof(float);
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}
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private:
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