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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 17:53:22 +02:00
video_core: Return safe values after an assert hits
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148a6418ed
commit
fc46ecddb3
@ -115,6 +115,7 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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default:
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UNIMPLEMENTED_MSG("Unhandled MUFU sub op={0:x}",
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static_cast<unsigned>(instr.sub_op.Value()));
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return Immediate(0);
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}
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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@ -62,6 +62,7 @@ void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation
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return op_b;
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default:
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UNIMPLEMENTED_MSG("Unimplemented logic operation={}", static_cast<u32>(logic_op));
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return Immediate(0);
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}
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}();
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@ -24,6 +24,7 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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return {GetRegister(instr.gpr39), Immediate(instr.alu.GetSignedImm20_20())};
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default:
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UNREACHABLE();
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return {Immediate(0), Immediate(0)};
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}
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}();
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const Node insert = GetRegister(instr.gpr8);
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@ -96,11 +96,10 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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return Operation(OperationCode::FCeil, PRECISE, value);
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case Tegra::Shader::F2fRoundingOp::Trunc:
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return Operation(OperationCode::FTrunc, PRECISE, value);
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default:
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UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
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static_cast<u32>(instr.conversion.f2f.rounding.Value()));
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break;
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}
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UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
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static_cast<u32>(instr.conversion.f2f.rounding.Value()));
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return Immediate(0);
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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@ -135,6 +134,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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default:
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UNIMPLEMENTED_MSG("Unimplemented F2I rounding mode {}",
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static_cast<u32>(instr.conversion.f2i.rounding.Value()));
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return Immediate(0);
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}
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}();
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const bool is_signed = instr.conversion.is_output_signed;
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@ -42,6 +42,7 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
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return {GetImmediate19(instr), GetRegister(instr.gpr39)};
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default:
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UNIMPLEMENTED_MSG("Unhandled FFMA instruction: {}", opcode->get().GetName());
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return {Immediate(0), Immediate(0)};
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}
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}();
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@ -42,9 +42,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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case OpCode::Id::XMAD_IMM:
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return {instr.xmad.merge_37, Immediate(static_cast<u32>(instr.xmad.imm20_16)),
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GetRegister(instr.gpr39)};
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default:
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UNIMPLEMENTED_MSG("Unhandled XMAD instruction: {}", opcode->get().GetName());
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}
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UNIMPLEMENTED_MSG("Unhandled XMAD instruction: {}", opcode->get().GetName());
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return {false, Immediate(0), Immediate(0)};
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}();
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if (instr.xmad.high_a) {
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@ -85,9 +85,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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NO_PRECISE, original_b, Immediate(16));
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return SignedOperation(OperationCode::IAdd, is_signed_c, NO_PRECISE, op_c, shifted_b);
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}
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default: {
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default:
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UNIMPLEMENTED_MSG("Unhandled XMAD mode: {}", static_cast<u32>(instr.xmad.mode.Value()));
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}
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return Immediate(0);
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}
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}();
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@ -353,6 +353,7 @@ private:
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return "samplerCube";
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default:
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UNREACHABLE();
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return "sampler2D";
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}
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}();
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if (sampler.IsArray())
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@ -506,6 +507,7 @@ private:
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return "// " + comment->GetText();
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}
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UNREACHABLE();
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return {};
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}
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std::string ApplyPrecise(Operation operation, const std::string& value) {
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@ -563,6 +565,7 @@ private:
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}
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}
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UNREACHABLE();
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return value;
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}
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std::string BitwiseCastResult(std::string value, Type type, bool needs_parenthesis = false) {
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@ -581,6 +584,7 @@ private:
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return "fromHalf2(" + value + ')';
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}
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UNREACHABLE();
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return value;
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}
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std::string GenerateUnary(Operation operation, const std::string& func, Type result_type,
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@ -697,6 +701,7 @@ private:
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}
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UNIMPLEMENTED_MSG("Unhandled output attribute: {}",
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static_cast<u32>(attribute));
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return "0";
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}
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}();
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@ -158,6 +158,7 @@ Node ShaderIR::ConvertIntegerSize(Node value, Tegra::Shader::Register::Size size
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return value;
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default:
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UNREACHABLE_MSG("Unimplemented conversion size: {}", static_cast<u32>(size));
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return value;
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}
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}
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@ -403,6 +404,7 @@ void ShaderIR::SetLocalMemory(BasicBlock& bb, Node address, Node value) {
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UNREACHABLE_MSG("Can't apply absolute to an unsigned integer");
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}
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UNREACHABLE_MSG("Unknown signed operation with code={}", static_cast<u32>(operation_code));
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return {};
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}
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} // namespace VideoCommon::Shader
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