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synced 2024-09-12 12:07:49 +02:00
shader: Implement ISETP.X
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@ -29,6 +29,49 @@ IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32
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}
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}
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}
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}
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IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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const IR::U32 zero{ir.Imm32(0)};
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const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
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const IR::U1 z_flag{ir.GetZFlag()};
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const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
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const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
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: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
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ir.ILessThan(operand_2, zero, true))};
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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case CompareOp::LessThan:
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return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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case CompareOp::Equal:
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return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
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case CompareOp::LessThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::GreaterThan: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
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ir.IGreaterThan(intermediate, zero, true))};
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const IR::U1 not_z{ir.LogicalNot(z_flag)};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
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}
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case CompareOp::NotEqual:
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return ir.LogicalOr(ir.INotEqual(intermediate, zero),
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ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
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case CompareOp::GreaterThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
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ir.IGreaterThanEqual(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::True:
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return ir.Imm1(true);
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default:
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
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IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
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BooleanOp bop) {
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BooleanOp bop) {
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switch (bop) {
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switch (bop) {
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@ -11,6 +11,10 @@ namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
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const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
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[[nodiscard]] IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, CompareOp compare_op,
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bool is_signed);
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop);
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const IR::U1& predicate_2, BooleanOp bop);
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@ -9,49 +9,6 @@
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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namespace {
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namespace {
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IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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const IR::U32 zero{ir.Imm32(0)};
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const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
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const IR::U1 z_flag{ir.GetZFlag()};
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const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
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const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
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: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
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ir.ILessThan(operand_2, zero, true))};
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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case CompareOp::LessThan:
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return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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case CompareOp::Equal:
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return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
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case CompareOp::LessThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::GreaterThan: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
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ir.IGreaterThan(intermediate, zero, true))};
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const IR::U1 not_z{ir.LogicalNot(z_flag)};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
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}
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case CompareOp::NotEqual:
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return ir.LogicalOr(ir.INotEqual(intermediate, zero),
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ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
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case CompareOp::GreaterThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
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ir.IGreaterThanEqual(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::True:
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return ir.Imm1(true);
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default:
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed, bool x) {
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CompareOp compare_op, bool is_signed, bool x) {
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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@ -9,6 +9,12 @@
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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namespace {
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namespace {
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IR::U1 IsetpCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed, bool x) {
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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: IntegerCompare(ir, operand_1, operand_2, compare_op, is_signed);
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}
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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union {
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union {
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u64 raw;
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u64 raw;
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@ -17,15 +23,18 @@ void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<43, 1, u64> x;
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BitField<45, 2, BooleanOp> bop;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, CompareOp> compare_op;
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BitField<49, 3, CompareOp> compare_op;
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} const isetp{insn};
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} const isetp{insn};
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const bool is_signed{isetp.is_signed != 0};
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const bool x{isetp.x != 0};
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const BooleanOp bop{isetp.bop};
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const BooleanOp bop{isetp.bop};
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const CompareOp compare_op{isetp.compare_op};
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const CompareOp compare_op{isetp.compare_op};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U1 comparison{IntegerCompare(v.ir, op_a, op_b, compare_op, isetp.is_signed != 0)};
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const IR::U1 comparison{IsetpCompare(v.ir, op_a, op_b, compare_op, is_signed, x)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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