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shader: Implement TLD4S.
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c7c518e280
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@ -124,6 +124,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/impl/texture_fetch.cpp
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frontend/maxwell/translate/impl/texture_fetch_swizzled.cpp
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frontend/maxwell/translate/impl/texture_gather_swizzled.cpp
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frontend/maxwell/translate/impl/texture_gather.cpp
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frontend/maxwell/translate/impl/vote.cpp
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frontend/maxwell/translate/impl/warp_shuffle.cpp
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@ -349,10 +349,6 @@ void TranslatorVisitor::TLD_b(u64) {
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ThrowNotImplemented(Opcode::TLD_b);
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}
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void TranslatorVisitor::TLD4S(u64) {
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ThrowNotImplemented(Opcode::TLD4S);
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}
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void TranslatorVisitor::TLDS(u64) {
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ThrowNotImplemented(Opcode::TLDS);
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}
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@ -0,0 +1,133 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <utility>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Precision : u64 {
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F32,
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F16,
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};
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enum class ComponentType : u64 {
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R = 0,
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G = 1,
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B = 2,
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A = 3,
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};
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union Encoding {
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u64 raw;
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BitField<55, 1, Precision> precision;
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BitField<52, 2, ComponentType> component_type;
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BitField<51, 1, u64> aoffi;
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BitField<50, 1, u64> dc;
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BitField<49, 1, u64> nodep;
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BitField<28, 8, IR::Reg> dest_reg_b;
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BitField<0, 8, IR::Reg> dest_reg_a;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<20, 8, IR::Reg> src_reg_b;
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BitField<36, 13, u64> cbuf_offset;
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};
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void CheckAlignment(IR::Reg reg, int alignment) {
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if (!IR::IsAligned(reg, alignment)) {
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throw NotImplementedException("Unaligned source register {}", reg);
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}
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}
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IR::Value MakeOffset(TranslatorVisitor& v, IR::Reg reg) {
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const IR::U32 value{v.X(reg)};
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return v.ir.CompositeConstruct(v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(6), true),
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v.ir.BitFieldExtract(value, v.ir.Imm32(8), v.ir.Imm32(6), true));
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}
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IR::Value Sample(TranslatorVisitor& v, u64 insn) {
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const Encoding tld4s{insn};
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const IR::U32 handle{v.ir.Imm32(static_cast<u32>(tld4s.cbuf_offset * 4))};
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const IR::Reg reg_a{tld4s.src_reg_a};
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const IR::Reg reg_b{tld4s.src_reg_b};
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IR::TextureInstInfo info{};
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if (tld4s.precision == Precision::F16) {
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info.relaxed_precision.Assign(1);
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}
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info.gather_component.Assign(static_cast<u32>(tld4s.component_type.Value()));
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info.type.Assign(tld4s.dc != 0 ? Shader::TextureType::Shadow2D : Shader::TextureType::Color2D);
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IR::Value coords;
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if (tld4s.aoffi != 0) {
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CheckAlignment(reg_a, 2);
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coords = v.ir.CompositeConstruct(v.F(reg_a), v.F(reg_a + 1));
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IR::Value offset = MakeOffset(v, reg_b);
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if (tld4s.dc != 0) {
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CheckAlignment(reg_b, 2);
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IR::F32 dref = v.F(reg_b + 1);
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return v.ir.ImageGatherDref(handle, coords, offset, {}, dref, info);
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}
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return v.ir.ImageGather(handle, coords, offset, {}, info);
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}
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if (tld4s.dc != 0) {
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CheckAlignment(reg_a, 2);
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coords = v.ir.CompositeConstruct(v.F(reg_a), v.F(reg_a + 1));
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IR::F32 dref = v.F(reg_b);
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return v.ir.ImageGatherDref(handle, coords, {}, {}, dref, info);
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}
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coords = v.ir.CompositeConstruct(v.F(reg_a), v.F(reg_b));
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return v.ir.ImageGather(handle, coords, {}, {}, info);
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}
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IR::Reg RegStoreComponent32(u64 insn, size_t index) {
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const Encoding tlds4{insn};
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switch (index) {
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case 0:
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return tlds4.dest_reg_a;
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case 1:
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CheckAlignment(tlds4.dest_reg_a, 2);
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return tlds4.dest_reg_a + 1;
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case 2:
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return tlds4.dest_reg_b;
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case 3:
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CheckAlignment(tlds4.dest_reg_b, 2);
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return tlds4.dest_reg_b + 1;
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}
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throw LogicError("Invalid store index {}", index);
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}
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void Store32(TranslatorVisitor& v, u64 insn, const IR::Value& sample) {
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for (size_t component = 0; component < 4; ++component) {
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const IR::Reg dest{RegStoreComponent32(insn, component)};
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v.F(dest, IR::F32{v.ir.CompositeExtract(sample, component)});
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}
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}
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IR::U32 Pack(TranslatorVisitor& v, const IR::F32& lhs, const IR::F32& rhs) {
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return v.ir.PackHalf2x16(v.ir.CompositeConstruct(lhs, rhs));
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}
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void Store16(TranslatorVisitor& v, u64 insn, const IR::Value& sample) {
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std::array<IR::F32, 4> swizzled;
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for (size_t component = 0; component < 4; ++component) {
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swizzled[component] = IR::F32{v.ir.CompositeExtract(sample, component)};
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}
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const Encoding tld4s{insn};
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v.X(tld4s.dest_reg_a, Pack(v, swizzled[0], swizzled[1]));
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v.X(tld4s.dest_reg_b, Pack(v, swizzled[2], swizzled[3]));
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}
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} // Anonymous namespace
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void TranslatorVisitor::TLD4S(u64 insn) {
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const IR::Value sample{Sample(*this, insn)};
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if (Encoding{insn}.precision == Precision::F32) {
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Store32(*this, insn, sample);
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} else {
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Store16(*this, insn, sample);
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}
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}
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} // namespace Shader::Maxwell
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