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ShaderGen: Implemented the fmul32i shader instruction.
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@ -90,6 +90,7 @@ union OpCode {
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enum class Id : u64 {
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TEXS = 0x6C,
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IPA = 0xE0,
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FMUL32_IMM = 0x1E,
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FFMA_IMM = 0x65,
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FFMA_CR = 0x93,
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FFMA_RC = 0xA3,
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@ -142,6 +143,7 @@ union OpCode {
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switch (op2) {
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case Id::IPA:
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case Id::FMUL32_IMM:
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return op2;
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}
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@ -235,6 +237,7 @@ union OpCode {
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info_table[Id::FMUL_R] = {Type::Arithmetic, "fmul_r"};
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FMUL32_IMM] = {Type::Arithmetic, "fmul32_imm"};
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info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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@ -309,7 +312,8 @@ union Instruction {
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BitField<39, 8, Register> gpr39;
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union {
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BitField<20, 19, u64> imm20;
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BitField<20, 19, u64> imm20_19;
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BitField<20, 32, u64> imm20_32;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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@ -317,14 +321,21 @@ union Instruction {
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BitField<50, 1, u64> abs_d;
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BitField<56, 1, u64> negate_imm;
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float GetImm20() const {
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float GetImm20_19() const {
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float result{};
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u32 imm{static_cast<u32>(imm20)};
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u32 imm{static_cast<u32>(imm20_19)};
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imm <<= 12;
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imm |= negate_imm ? 0x80000000 : 0;
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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float GetImm20_32() const {
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float result{};
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u32 imm{static_cast<u32>(imm20_32)};
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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} alu;
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union {
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@ -190,9 +190,14 @@ private:
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}
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}
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/// Generates code representing an immediate value
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static std::string GetImmediate(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20());
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/// Generates code representing a 19-bit immediate value
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static std::string GetImmediate19(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20_19());
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}
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/// Generates code representing a 32-bit immediate value
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static std::string GetImmediate32(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20_32());
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}
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/// Generates code representing a temporary (GPR) register.
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@ -276,7 +281,7 @@ private:
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std::string op_b = instr.alu.negate_b ? "-" : "";
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if (instr.is_b_imm) {
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op_b += GetImmediate(instr);
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op_b += GetImmediate19(instr);
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} else {
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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@ -296,6 +301,11 @@ private:
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SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::FMUL32_IMM: {
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// fmul32i doesn't have abs or neg bits.
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SetDest(0, dest, GetRegister(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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@ -364,7 +374,7 @@ private:
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break;
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}
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case OpCode::Id::FFMA_IMM: {
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op_b += GetImmediate(instr);
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op_b += GetImmediate19(instr);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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@ -593,7 +603,7 @@ private:
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std::set<Attribute::Index> declr_input_attribute;
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std::set<Attribute::Index> declr_output_attribute;
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std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
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};
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}; // namespace Decompiler
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std::string GetCommonDeclarations() {
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return "bool exec_shader();";
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