mirror of
https://github.com/citra-mirror/citra.git
synced 2024-08-20 10:23:23 +02:00
dyncom: Make Load/Store instructions support big endian
This commit is contained in:
parent
f280806214
commit
9fdb311d6e
@ -4362,30 +4362,30 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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if (BIT(inst, 22) && !BIT(inst, 15)) {
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for (int i = 0; i < 13; i++) {
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if(BIT(inst, i)) {
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cpu->Reg[i] = Memory::Read32(addr);
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cpu->Reg[i] = ReadMemory32(cpu, addr);
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addr += 4;
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}
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}
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if (BIT(inst, 13)) {
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if (cpu->Mode == USER32MODE)
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cpu->Reg[13] = Memory::Read32(addr);
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cpu->Reg[13] = ReadMemory32(cpu, addr);
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else
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cpu->Reg_usr[0] = Memory::Read32(addr);
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cpu->Reg_usr[0] = ReadMemory32(cpu, addr);
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addr += 4;
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}
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if (BIT(inst, 14)) {
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if (cpu->Mode == USER32MODE)
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cpu->Reg[14] = Memory::Read32(addr);
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cpu->Reg[14] = ReadMemory32(cpu, addr);
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else
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cpu->Reg_usr[1] = Memory::Read32(addr);
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cpu->Reg_usr[1] = ReadMemory32(cpu, addr);
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addr += 4;
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}
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} else if (!BIT(inst, 22)) {
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for(int i = 0; i < 16; i++ ){
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if(BIT(inst, i)){
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unsigned int ret = Memory::Read32(addr);
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unsigned int ret = ReadMemory32(cpu, addr);
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// For armv5t, should enter thumb when bits[0] is non-zero.
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if(i == 15){
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@ -4400,7 +4400,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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} else if (BIT(inst, 22) && BIT(inst, 15)) {
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for(int i = 0; i < 15; i++ ){
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if(BIT(inst, i)){
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cpu->Reg[i] = Memory::Read32(addr);
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cpu->Reg[i] = ReadMemory32(cpu, addr);
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addr += 4;
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}
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}
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@ -4411,7 +4411,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LOAD_NZCVT;
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}
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cpu->Reg[15] = Memory::Read32(addr);
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cpu->Reg[15] = ReadMemory32(cpu, addr);
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}
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if (BIT(inst, 15)) {
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@ -4445,20 +4445,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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LDR_INST:
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{
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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//if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read32(addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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unsigned int value = ReadMemory32(cpu, addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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// For armv5t, should enter thumb when bits[0] is non-zero.
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cpu->TFlag = value & 0x1;
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cpu->Reg[15] &= 0xFFFFFFFE;
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INC_PC(sizeof(ldst_inst));
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goto DISPATCH;
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}
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//}
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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// For armv5t, should enter thumb when bits[0] is non-zero.
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cpu->TFlag = value & 0x1;
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cpu->Reg[15] &= 0xFFFFFFFE;
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INC_PC(sizeof(ldst_inst));
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goto DISPATCH;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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@ -4471,7 +4469,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read32(addr);
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unsigned int value = ReadMemory32(cpu, addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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@ -4554,8 +4552,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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// Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read32(addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = Memory::Read32(addr + 4);
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// The 3DS doesn't have LPAE (Large Physical Access Extension), so it
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// wouldn't do this as a single read.
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cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = ReadMemory32(cpu, addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = ReadMemory32(cpu, addr + 4);
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// No dispatch since this operation should not modify R15
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}
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@ -4574,7 +4574,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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RD = Memory::Read32(read_addr);
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RD = ReadMemory32(cpu, read_addr);
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(generic_arm_inst));
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goto DISPATCH;
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@ -4614,7 +4614,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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RD = Memory::Read16(read_addr);
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RD = ReadMemory16(cpu, read_addr);
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(generic_arm_inst));
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goto DISPATCH;
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@ -4634,8 +4634,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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add_exclusive_addr(cpu, read_addr);
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cpu->exclusive_state = 1;
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RD = Memory::Read32(read_addr);
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RD2 = Memory::Read32(read_addr + 4);
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RD = ReadMemory32(cpu, read_addr);
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RD2 = ReadMemory32(cpu, read_addr + 4);
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if (inst_cream->Rd == 15) {
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INC_PC(sizeof(generic_arm_inst));
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@ -4652,7 +4652,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read16(addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ReadMemory16(cpu, addr);
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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INC_PC(sizeof(ldst_inst));
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goto DISPATCH;
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@ -4688,7 +4689,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read16(addr);
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unsigned int value = ReadMemory16(cpu, addr);
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if (BIT(value, 15)) {
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value |= 0xffff0000;
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}
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@ -4709,7 +4711,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
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unsigned int value = Memory::Read32(addr);
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unsigned int value = ReadMemory32(cpu, addr);
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cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
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if (BITS(inst_cream->inst, 12, 15) == 15) {
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@ -6010,36 +6012,36 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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if (BIT(inst_cream->inst, 22) == 1) {
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for (int i = 0; i < 13; i++) {
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if (BIT(inst_cream->inst, i)) {
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Memory::Write32(addr, cpu->Reg[i]);
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WriteMemory32(cpu, addr, cpu->Reg[i]);
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addr += 4;
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}
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}
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if (BIT(inst_cream->inst, 13)) {
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if (cpu->Mode == USER32MODE)
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Memory::Write32(addr, cpu->Reg[13]);
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WriteMemory32(cpu, addr, cpu->Reg[13]);
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else
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Memory::Write32(addr, cpu->Reg_usr[0]);
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WriteMemory32(cpu, addr, cpu->Reg_usr[0]);
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addr += 4;
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}
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if (BIT(inst_cream->inst, 14)) {
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if (cpu->Mode == USER32MODE)
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Memory::Write32(addr, cpu->Reg[14]);
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WriteMemory32(cpu, addr, cpu->Reg[14]);
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else
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Memory::Write32(addr, cpu->Reg_usr[1]);
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WriteMemory32(cpu, addr, cpu->Reg_usr[1]);
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addr += 4;
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}
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if (BIT(inst_cream->inst, 15)) {
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Memory::Write32(addr, cpu->Reg_usr[1] + 8);
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WriteMemory32(cpu, addr, cpu->Reg_usr[1] + 8);
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}
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} else {
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for (int i = 0; i < 15; i++) {
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if (BIT(inst_cream->inst, i)) {
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if (i == Rn)
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Memory::Write32(addr, old_RN);
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WriteMemory32(cpu, addr, old_RN);
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else
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Memory::Write32(addr, cpu->Reg[i]);
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WriteMemory32(cpu, addr, cpu->Reg[i]);
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addr += 4;
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}
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@ -6047,7 +6049,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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// Check PC reg
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if (BIT(inst_cream->inst, 15))
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Memory::Write32(addr, cpu->Reg_usr[1] + 8);
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WriteMemory32(cpu, addr, cpu->Reg_usr[1] + 8);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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@ -6080,7 +6082,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
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unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
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Memory::Write32(addr, value);
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WriteMemory32(cpu, addr, value);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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@ -6143,10 +6145,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
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unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
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Memory::Write32(addr, value);
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value = cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1];
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Memory::Write32(addr + 4, value);
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// The 3DS doesn't have the Large Physical Access Extension (LPAE)
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// so STRD wouldn't store these as a single write.
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WriteMemory32(cpu, addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);
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WriteMemory32(cpu, addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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@ -6163,7 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]);
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WriteMemory32(cpu, write_addr, RM);
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RD = 0;
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} else {
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// Failed to write due to mutex access
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@ -6207,8 +6209,16 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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Memory::Write32(write_addr, cpu->Reg[inst_cream->Rm]);
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Memory::Write32(write_addr + 4, cpu->Reg[inst_cream->Rm + 1]);
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const u32 rt = cpu->Reg[inst_cream->Rm + 0];
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const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
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u64 value;
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if (InBigEndianMode(cpu))
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value = (((u64)rt << 32) | rt2);
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else
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value = (((u64)rt2 << 32) | rt);
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WriteMemory64(cpu, write_addr, value);
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RD = 0;
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}
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else {
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@ -6231,7 +6241,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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remove_exclusive(cpu, write_addr);
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cpu->exclusive_state = 0;
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Memory::Write16(write_addr, cpu->Reg[inst_cream->Rm]);
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WriteMemory16(cpu, write_addr, RM);
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RD = 0;
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} else {
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// Failed to write due to mutex access
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@ -6250,7 +6260,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
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unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
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Memory::Write16(addr, value);
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WriteMemory16(cpu, addr, value);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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@ -6264,7 +6274,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
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unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
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Memory::Write32(addr, value);
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WriteMemory32(cpu, addr, value);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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@ -6323,8 +6333,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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swp_inst* inst_cream = (swp_inst*)inst_base->component;
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addr = RN;
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unsigned int value = Memory::Read32(addr);
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Memory::Write32(addr, RM);
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unsigned int value = ReadMemory32(cpu, addr);
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WriteMemory32(cpu, addr, RM);
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RD = value;
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}
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@ -201,3 +201,9 @@ u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred)
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*saturation_occurred = false;
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return (u32)value;
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}
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// Whether or not the given CPU is in big endian mode (E bit is set)
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bool InBigEndianMode(ARMul_State* cpu)
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{
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return (cpu->Cpsr & (1 << 9)) != 0;
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}
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@ -18,7 +18,6 @@
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#pragma once
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/armmmu.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/skyeye_defs.h"
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@ -356,3 +355,5 @@ extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
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extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
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extern u32 ARMul_SignedSatQ(s32, u8, bool*);
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extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
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extern bool InBigEndianMode(ARMul_State*);
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@ -20,6 +20,9 @@
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#pragma once
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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// Register numbers in the MMU
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enum
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{
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@ -54,3 +57,55 @@ enum
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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};
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// Reads data in big/little endian format based on the
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// state of the E (endian) bit in the emulated CPU's APSR.
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inline u16 ReadMemory16(ARMul_State* cpu, u32 address) {
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u16 data = Memory::Read16(address);
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if (InBigEndianMode(cpu))
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data = Common::swap16(data);
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return data;
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}
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inline u32 ReadMemory32(ARMul_State* cpu, u32 address) {
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u32 data = Memory::Read32(address);
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if (InBigEndianMode(cpu))
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data = Common::swap32(data);
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return data;
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}
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inline u64 ReadMemory64(ARMul_State* cpu, u32 address) {
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u64 data = Memory::Read64(address);
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if (InBigEndianMode(cpu))
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data = Common::swap64(data);
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return data;
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}
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// Writes data in big/little endian format based on the
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// state of the E (endian) bit in the emulated CPU's APSR.
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inline void WriteMemory16(ARMul_State* cpu, u32 address, u16 data) {
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if (InBigEndianMode(cpu))
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data = Common::swap16(data);
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Memory::Write16(address, data);
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}
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inline void WriteMemory32(ARMul_State* cpu, u32 address, u32 data) {
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if (InBigEndianMode(cpu))
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data = Common::swap32(data);
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Memory::Write32(address, data);
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}
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inline void WriteMemory64(ARMul_State* cpu, u32 address, u64 data) {
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if (InBigEndianMode(cpu))
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data = Common::swap64(data);
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Memory::Write64(address, data);
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}
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@ -1388,12 +1388,20 @@ VSTR_INST:
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if (inst_cream->single)
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{
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Memory::Write32(addr, cpu->ExtReg[inst_cream->d]);
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WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d]);
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}
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else
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{
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Memory::Write32(addr, cpu->ExtReg[inst_cream->d*2]);
|
||||
Memory::Write32(addr + 4, cpu->ExtReg[inst_cream->d*2+1]);
|
||||
const u32 word1 = cpu->ExtReg[inst_cream->d*2+0];
|
||||
const u32 word2 = cpu->ExtReg[inst_cream->d*2+1];
|
||||
|
||||
if (InBigEndianMode(cpu)) {
|
||||
WriteMemory32(cpu, addr + 0, word2);
|
||||
WriteMemory32(cpu, addr + 4, word1);
|
||||
} else {
|
||||
WriteMemory32(cpu, addr + 0, word1);
|
||||
WriteMemory32(cpu, addr + 4, word2);
|
||||
}
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
@ -1447,17 +1455,27 @@ VPUSH_INST:
|
||||
{
|
||||
if (inst_cream->single)
|
||||
{
|
||||
Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
|
||||
WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d+i]);
|
||||
addr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
|
||||
Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
|
||||
const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0];
|
||||
const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1];
|
||||
|
||||
if (InBigEndianMode(cpu)) {
|
||||
WriteMemory32(cpu, addr + 0, word2);
|
||||
WriteMemory32(cpu, addr + 4, word1);
|
||||
} else {
|
||||
WriteMemory32(cpu, addr + 0, word1);
|
||||
WriteMemory32(cpu, addr + 4, word2);
|
||||
}
|
||||
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
cpu->Reg[R13] = cpu->Reg[R13] - inst_cream->imm32;
|
||||
|
||||
cpu->Reg[R13] -= inst_cream->imm32;
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(vpush_inst));
|
||||
@ -1516,13 +1534,22 @@ VSTM_INST: /* encoding 1 */
|
||||
{
|
||||
if (inst_cream->single)
|
||||
{
|
||||
Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
|
||||
WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d+i]);
|
||||
addr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
|
||||
Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
|
||||
const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0];
|
||||
const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1];
|
||||
|
||||
if (InBigEndianMode(cpu)) {
|
||||
WriteMemory32(cpu, addr + 0, word2);
|
||||
WriteMemory32(cpu, addr + 4, word1);
|
||||
} else {
|
||||
WriteMemory32(cpu, addr + 0, word1);
|
||||
WriteMemory32(cpu, addr + 4, word2);
|
||||
}
|
||||
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
@ -1575,8 +1602,6 @@ VPOP_INST:
|
||||
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
|
||||
CHECK_VFP_ENABLED;
|
||||
|
||||
unsigned int value1, value2;
|
||||
|
||||
vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
|
||||
|
||||
addr = cpu->Reg[R13];
|
||||
@ -1585,20 +1610,26 @@ VPOP_INST:
|
||||
{
|
||||
if (inst_cream->single)
|
||||
{
|
||||
value1 = Memory::Read32(addr);
|
||||
cpu->ExtReg[inst_cream->d+i] = value1;
|
||||
cpu->ExtReg[inst_cream->d+i] = ReadMemory32(cpu, addr);
|
||||
addr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
value1 = Memory::Read32(addr);
|
||||
value2 = Memory::Read32(addr + 4);
|
||||
cpu->ExtReg[(inst_cream->d+i)*2] = value1;
|
||||
cpu->ExtReg[(inst_cream->d+i)*2 + 1] = value2;
|
||||
const u32 word1 = ReadMemory32(cpu, addr + 0);
|
||||
const u32 word2 = ReadMemory32(cpu, addr + 4);
|
||||
|
||||
if (InBigEndianMode(cpu)) {
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+0] = word2;
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+1] = word1;
|
||||
} else {
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+0] = word1;
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+1] = word2;
|
||||
}
|
||||
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
cpu->Reg[R13] = cpu->Reg[R13] + inst_cream->imm32;
|
||||
cpu->Reg[R13] += inst_cream->imm32;
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
INC_PC(sizeof(vpop_inst));
|
||||
@ -1653,16 +1684,20 @@ VLDR_INST:
|
||||
|
||||
if (inst_cream->single)
|
||||
{
|
||||
cpu->ExtReg[inst_cream->d] = Memory::Read32(addr);
|
||||
cpu->ExtReg[inst_cream->d] = ReadMemory32(cpu, addr);
|
||||
}
|
||||
else
|
||||
{
|
||||
unsigned int word1, word2;
|
||||
word1 = Memory::Read32(addr);
|
||||
word2 = Memory::Read32(addr + 4);
|
||||
const u32 word1 = ReadMemory32(cpu, addr + 0);
|
||||
const u32 word2 = ReadMemory32(cpu, addr + 4);
|
||||
|
||||
cpu->ExtReg[inst_cream->d*2] = word1;
|
||||
cpu->ExtReg[inst_cream->d*2+1] = word2;
|
||||
if (InBigEndianMode(cpu)) {
|
||||
cpu->ExtReg[inst_cream->d*2+0] = word2;
|
||||
cpu->ExtReg[inst_cream->d*2+1] = word1;
|
||||
} else {
|
||||
cpu->ExtReg[inst_cream->d*2+0] = word1;
|
||||
cpu->ExtReg[inst_cream->d*2+1] = word2;
|
||||
}
|
||||
}
|
||||
}
|
||||
cpu->Reg[15] += GET_INST_SIZE(cpu);
|
||||
@ -1722,13 +1757,22 @@ VLDM_INST:
|
||||
{
|
||||
if (inst_cream->single)
|
||||
{
|
||||
cpu->ExtReg[inst_cream->d+i] = Memory::Read32(addr);
|
||||
cpu->ExtReg[inst_cream->d+i] = ReadMemory32(cpu, addr);
|
||||
addr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu->ExtReg[(inst_cream->d+i)*2] = Memory::Read32(addr);
|
||||
cpu->ExtReg[(inst_cream->d+i)*2 + 1] = Memory::Read32(addr + 4);
|
||||
const u32 word1 = ReadMemory32(cpu, addr + 0);
|
||||
const u32 word2 = ReadMemory32(cpu, addr + 4);
|
||||
|
||||
if (InBigEndianMode(cpu)) {
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+0] = word2;
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+1] = word1;
|
||||
} else {
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+0] = word1;
|
||||
cpu->ExtReg[(inst_cream->d+i)*2+1] = word2;
|
||||
}
|
||||
|
||||
addr += 8;
|
||||
}
|
||||
}
|
||||
|
@ -147,6 +147,7 @@ inline void Write(VAddr addr, T data);
|
||||
u8 Read8(VAddr addr);
|
||||
u16 Read16(VAddr addr);
|
||||
u32 Read32(VAddr addr);
|
||||
u64 Read64(VAddr addr);
|
||||
|
||||
u32 Read8_ZX(VAddr addr);
|
||||
u32 Read16_ZX(VAddr addr);
|
||||
|
@ -245,6 +245,12 @@ u32 Read32(const VAddr addr) {
|
||||
return (u32)data;
|
||||
}
|
||||
|
||||
u64 Read64(const VAddr addr) {
|
||||
u64_le data = 0;
|
||||
Read<u64_le>(data, addr);
|
||||
return (u64)data;
|
||||
}
|
||||
|
||||
u32 Read8_ZX(const VAddr addr) {
|
||||
return (u32)Read8(addr);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user