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Merge pull request #2400 from FernandoS27/corret-kepler-mem
Implement Kepler Memory on both Linear and BlockLinear.
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commit
01100f8afd
@ -10,6 +10,7 @@
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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@ -27,30 +28,46 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
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switch (method_call.method) {
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case KEPLERMEMORY_REG_INDEX(exec): {
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state.write_offset = 0;
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ProcessExec();
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break;
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}
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case KEPLERMEMORY_REG_INDEX(data): {
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ProcessData(method_call.argument);
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ProcessData(method_call.argument, method_call.IsLastCall());
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break;
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}
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}
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}
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void KeplerMemory::ProcessData(u32 data) {
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ASSERT_MSG(regs.exec.linear, "Non-linear uploads are not supported");
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ASSERT(regs.dest.x == 0 && regs.dest.y == 0 && regs.dest.z == 0);
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void KeplerMemory::ProcessExec() {
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state.write_offset = 0;
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state.copy_size = regs.line_length_in * regs.line_count;
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state.inner_buffer.resize(state.copy_size);
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}
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// We have to invalidate the destination region to evict any outdated surfaces from the cache.
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// We do this before actually writing the new data because the destination address might
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// contain a dirty surface that will have to be written back to memory.
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const GPUVAddr address{regs.dest.Address() + state.write_offset * sizeof(u32)};
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rasterizer.InvalidateRegion(ToCacheAddr(memory_manager.GetPointer(address)), sizeof(u32));
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memory_manager.Write<u32>(address, data);
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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state.write_offset++;
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void KeplerMemory::ProcessData(u32 data, bool is_last_call) {
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const u32 sub_copy_size = std::min(4U, state.copy_size - state.write_offset);
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std::memcpy(&state.inner_buffer[state.write_offset], ®s.data, sub_copy_size);
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state.write_offset += sub_copy_size;
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if (is_last_call) {
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const GPUVAddr address{regs.dest.Address()};
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if (regs.exec.linear != 0) {
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memory_manager.WriteBlock(address, state.inner_buffer.data(), state.copy_size);
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} else {
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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std::vector<u8> tmp_buffer(dst_size);
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
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regs.dest.y, regs.dest.BlockHeight(), state.copy_size,
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state.inner_buffer.data(), tmp_buffer.data());
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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}
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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}
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}
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} // namespace Tegra::Engines
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@ -6,6 +6,7 @@
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#include <array>
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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@ -51,7 +52,11 @@ public:
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u32 address_high;
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u32 address_low;
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u32 pitch;
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u32 block_dimensions;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 width;
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u32 height;
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u32 depth;
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@ -63,6 +68,18 @@ public:
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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u32 BlockWidth() const {
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return 1U << block_width.Value();
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}
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u32 BlockHeight() const {
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return 1U << block_height.Value();
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}
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u32 BlockDepth() const {
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return 1U << block_depth.Value();
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}
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} dest;
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struct {
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@ -81,6 +98,8 @@ public:
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struct {
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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} state{};
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private:
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@ -88,7 +107,8 @@ private:
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VideoCore::RasterizerInterface& rasterizer;
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MemoryManager& memory_manager;
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void ProcessData(u32 data);
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void ProcessExec();
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void ProcessData(u32 data, bool is_last_call);
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -288,6 +288,29 @@ void UnswizzleSubrect(u32 subrect_width, u32 subrect_height, u32 dest_pitch, u32
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}
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}
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void SwizzleKepler(const u32 width, const u32 height, const u32 dst_x, const u32 dst_y,
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const u32 block_height, const std::size_t copy_size, const u8* source_data,
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u8* swizzle_data) {
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const u32 image_width_in_gobs{(width + gob_size_x - 1) / gob_size_x};
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std::size_t count = 0;
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for (std::size_t y = dst_y; y < height && count < copy_size; ++y) {
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const std::size_t gob_address_y =
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(y / (gob_size_y * block_height)) * gob_size * block_height * image_width_in_gobs +
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((y % (gob_size_y * block_height)) / gob_size_y) * gob_size;
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const auto& table = legacy_swizzle_table[y % gob_size_y];
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for (std::size_t x = dst_x; x < width && count < copy_size; ++x) {
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const std::size_t gob_address =
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gob_address_y + (x / gob_size_x) * gob_size * block_height;
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const std::size_t swizzled_offset = gob_address + table[x % gob_size_x];
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const u8* source_line = source_data + count;
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u8* dest_addr = swizzle_data + swizzled_offset;
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count++;
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std::memcpy(dest_addr, source_line, 1);
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}
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}
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}
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std::vector<u8> DecodeTexture(const std::vector<u8>& texture_data, TextureFormat format, u32 width,
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u32 height) {
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std::vector<u8> rgba_data;
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@ -51,4 +51,8 @@ void UnswizzleSubrect(u32 subrect_width, u32 subrect_height, u32 dest_pitch, u32
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u32 bytes_per_pixel, u8* swizzled_data, u8* unswizzled_data, u32 block_height,
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u32 offset_x, u32 offset_y);
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void SwizzleKepler(const u32 width, const u32 height, const u32 dst_x, const u32 dst_y,
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const u32 block_height, const std::size_t copy_size, const u8* source_data,
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u8* swizzle_data);
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} // namespace Tegra::Texture
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