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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #2407 from FernandoS27/f2f
Do some corrections in conversion shader instructions.
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commit
da0c3bc658
@ -937,21 +937,34 @@ union Instruction {
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} iset;
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union {
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BitField<8, 2, Register::Size> dest_size;
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BitField<10, 2, Register::Size> src_size;
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BitField<12, 1, u64> is_output_signed;
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BitField<13, 1, u64> is_input_signed;
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BitField<41, 2, u64> selector;
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BitField<41, 2, u64> selector; // i2i and i2f only
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BitField<45, 1, u64> negate_a;
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BitField<49, 1, u64> abs_a;
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BitField<10, 2, Register::Size> src_size;
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BitField<13, 1, u64> is_input_signed;
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BitField<8, 2, Register::Size> dst_size;
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BitField<12, 1, u64> is_output_signed;
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union {
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BitField<39, 2, u64> tab5cb8_2;
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} i2f;
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union {
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BitField<39, 2, F2iRoundingOp> rounding;
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} f2i;
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union {
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BitField<39, 4, F2fRoundingOp> rounding;
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BitField<8, 2, Register::Size> src_size;
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BitField<10, 2, Register::Size> dst_size;
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BitField<39, 4, u64> rounding;
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// H0, H1 extract for F16 missing
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BitField<41, 1, u64> selector; // Guessed as some games set it, TODO: reverse this value
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F2fRoundingOp GetRoundingMode() const {
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constexpr u64 rounding_mask = 0x0B;
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return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
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}
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} f2f;
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} conversion;
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union {
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@ -1734,7 +1747,7 @@ private:
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INST("0011100-00101---", Id::SHR_IMM, Type::Shift, "SHR_IMM"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("0011101-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("0100110010111---", Id::I2F_C, Type::Conversion, "I2F_C"),
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INST("0101110010111---", Id::I2F_R, Type::Conversion, "I2F_R"),
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INST("0011100-10111---", Id::I2F_IMM, Type::Conversion, "I2F_IMM"),
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@ -18,13 +18,29 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2I_R: {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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const bool input_signed = instr.conversion.is_input_signed;
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const bool output_signed = instr.conversion.is_output_signed;
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Node value = GetRegister(instr.gpr20);
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Node value = [&]() {
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2I_R:
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return GetRegister(instr.gpr20);
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case OpCode::Id::I2I_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::I2I_IMM:
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return Immediate(instr.alu.GetSignedImm20_20());
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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value = ConvertIntegerSize(value, instr.conversion.src_size, input_signed);
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value = GetOperandAbsNegInteger(value, instr.conversion.abs_a, instr.conversion.negate_a,
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@ -38,17 +54,24 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_C: {
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UNIMPLEMENTED_IF(instr.conversion.dest_size != Register::Size::Word);
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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Node value = [&]() {
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if (instr.is_b_gpr) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2F_R:
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return GetRegister(instr.gpr20);
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} else {
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case OpCode::Id::I2F_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::I2F_IMM:
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return Immediate(instr.alu.GetSignedImm20_20());
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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const bool input_signed = instr.conversion.is_input_signed;
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@ -62,24 +85,31 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::F2F_R:
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case OpCode::Id::F2F_C: {
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UNIMPLEMENTED_IF(instr.conversion.dest_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.src_size != Register::Size::Word);
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.f2f.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.f2f.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2F is not implemented");
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Node value = [&]() {
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if (instr.is_b_gpr) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::F2F_R:
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return GetRegister(instr.gpr20);
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} else {
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case OpCode::Id::F2F_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::F2F_IMM:
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return GetImmediate19(instr);
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = [&]() {
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switch (instr.conversion.f2f.rounding) {
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switch (instr.conversion.f2f.GetRoundingMode()) {
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case Tegra::Shader::F2fRoundingOp::None:
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return value;
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case Tegra::Shader::F2fRoundingOp::Round:
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@ -102,15 +132,22 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::F2I_R:
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case OpCode::Id::F2I_C: {
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case OpCode::Id::F2I_C:
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case OpCode::Id::F2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2I is not implemented");
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Node value = [&]() {
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if (instr.is_b_gpr) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::F2I_R:
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return GetRegister(instr.gpr20);
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} else {
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case OpCode::Id::F2I_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::F2I_IMM:
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return GetImmediate19(instr);
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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@ -134,7 +171,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}();
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const bool is_signed = instr.conversion.is_output_signed;
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value = SignedOperation(OperationCode::ICastFloat, is_signed, PRECISE, value);
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value = ConvertIntegerSize(value, instr.conversion.dest_size, is_signed);
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value = ConvertIntegerSize(value, instr.conversion.dst_size, is_signed);
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SetRegister(bb, instr.gpr0, value);
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break;
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