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Merge pull request #422 from bunnei/shader-mov
Shader instructions MOV_C, MOV_R, and several minor GPU things
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commit
225ff1130f
@ -208,6 +208,16 @@ void Maxwell3D::DrawArrays() {
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const bool is_indexed{regs.index_array.count && !regs.vertex_buffer.count};
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const bool is_indexed{regs.index_array.count && !regs.vertex_buffer.count};
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(is_indexed);
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(is_indexed);
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// TODO(bunnei): Below, we reset vertex count so that we can use these registers to determine if
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// the game is trying to draw indexed or direct mode. This needs to be verified on HW still -
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// it's possible that it is incorrect and that there is some other register used to specify the
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// drawing mode.
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if (is_indexed) {
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regs.index_array.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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}
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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@ -310,6 +310,7 @@ public:
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SHR_C,
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SHR_C,
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SHR_R,
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SHR_R,
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SHR_IMM,
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SHR_IMM,
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FMNMX,
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FSETP_C, // Set Predicate
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FSETP_C, // Set Predicate
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FSETP_R,
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FSETP_R,
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FSETP_IMM,
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FSETP_IMM,
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@ -460,6 +461,7 @@ private:
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INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
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INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
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INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
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INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
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INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
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INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
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INST("0101110001100---", Id::FMNMX, Type::Arithmetic, "FMNMX"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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@ -664,6 +664,12 @@ private:
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}
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}
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switch (opcode->GetId()) {
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switch (opcode->GetId()) {
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case OpCode::Id::MOV_C:
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case OpCode::Id::MOV_R: {
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regs.SetRegisterToFloat(instr.gpr0, 0, op_b, 1, 1);
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break;
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}
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case OpCode::Id::MOV32_IMM: {
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case OpCode::Id::MOV32_IMM: {
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// mov32i doesn't have abs or neg bits.
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// mov32i doesn't have abs or neg bits.
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regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1);
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regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1);
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@ -36,6 +36,18 @@ inline GLenum VertexType(Maxwell::VertexAttribute attrib) {
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return {};
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return {};
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}
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}
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case Maxwell::VertexAttribute::Type::SignedNorm: {
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switch (attrib.size) {
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case Maxwell::VertexAttribute::Size::Size_8_8_8_8:
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return GL_BYTE;
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}
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented vertex size={}", attrib.SizeString());
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UNREACHABLE();
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return {};
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}
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case Maxwell::VertexAttribute::Type::Float:
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case Maxwell::VertexAttribute::Type::Float:
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return GL_FLOAT;
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return GL_FLOAT;
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}
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}
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