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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 20:03:25 +02:00
shader_decode: Use BitfieldExtract instead of shift + and
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52223313b1
commit
2faad9bf23
@ -985,6 +985,11 @@ private:
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Type::Int);
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}
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template <Type type>
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std::string BitfieldExtract(Operation operation) {
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return GenerateTernary(operation, "bitfieldExtract", type, type, Type::Int, Type::Int);
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}
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template <Type type>
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std::string BitCount(Operation operation) {
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return GenerateUnary(operation, "bitCount", type, type, false);
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@ -1369,6 +1374,7 @@ private:
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&GLSLDecompiler::BitwiseXor<Type::Int>,
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&GLSLDecompiler::BitwiseNot<Type::Int>,
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&GLSLDecompiler::BitfieldInsert<Type::Int>,
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&GLSLDecompiler::BitfieldExtract<Type::Int>,
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&GLSLDecompiler::BitCount<Type::Int>,
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&GLSLDecompiler::Add<Type::Uint>,
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@ -1386,6 +1392,7 @@ private:
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&GLSLDecompiler::BitwiseXor<Type::Uint>,
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&GLSLDecompiler::BitwiseNot<Type::Uint>,
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&GLSLDecompiler::BitfieldInsert<Type::Uint>,
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&GLSLDecompiler::BitfieldExtract<Type::Uint>,
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&GLSLDecompiler::BitCount<Type::Uint>,
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&GLSLDecompiler::Add<Type::HalfFloat>,
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@ -57,10 +57,9 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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case IAdd3Height::None:
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return value;
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case IAdd3Height::LowerHalfWord:
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return Operation(OperationCode::IBitwiseAnd, NO_PRECISE, value, Immediate(0xffff));
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return BitfieldExtract(value, 0, 16);
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case IAdd3Height::UpperHalfWord:
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return Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, value,
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Immediate(16));
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return BitfieldExtract(value, 16, 16);
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default:
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UNIMPLEMENTED_MSG("Unhandled IADD3 height: {}", static_cast<u32>(height));
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return Immediate(0);
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@ -28,13 +28,8 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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}
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}();
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const Node insert = GetRegister(instr.gpr8);
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const Node offset =
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Operation(OperationCode::UBitwiseAnd, NO_PRECISE, packed_shift, Immediate(0xff));
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Node bits =
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Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, packed_shift, Immediate(8));
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bits = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, bits, Immediate(0xff));
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const Node offset = BitfieldExtract(packed_shift, 0, 8);
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const Node bits = BitfieldExtract(packed_shift, 8, 8);
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const Node value =
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Operation(OperationCode::UBitfieldInsert, PRECISE, base, insert, offset, bits);
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@ -27,20 +27,18 @@ u32 ShaderIR::DecodeRegisterSetPredicate(BasicBlock& bb, u32 pc) {
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return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
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}
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}();
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const Node mask =
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Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, GetRegister(instr.gpr8),
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Immediate(static_cast<u32>(instr.r2p.byte)));
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const Node mask = GetRegister(instr.gpr8);
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const auto offset = static_cast<u32>(instr.r2p.byte) * 8;
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constexpr u32 programmable_preds = 7;
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for (u64 pred = 0; pred < programmable_preds; ++pred) {
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const Node shift = Immediate(1u << static_cast<u32>(pred));
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const auto shift = static_cast<u32>(pred);
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const Node apply_compare =
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Operation(OperationCode::UBitwiseAnd, NO_PRECISE, apply_mask, shift);
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const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
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const Node condition =
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Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
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const Node value_compare = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, mask, shift);
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const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
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const Node value = Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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@ -88,21 +88,15 @@ u32 ShaderIR::DecodeVideo(BasicBlock& bb, u32 pc) {
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Node ShaderIR::GetVideoOperand(Node op, bool is_chunk, bool is_signed,
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Tegra::Shader::VideoType type, u64 byte_height) {
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if (!is_chunk) {
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const auto offset = static_cast<u32>(byte_height * 8);
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const Node shift = SignedOperation(OperationCode::ILogicalShiftRight, is_signed, NO_PRECISE,
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op, Immediate(offset));
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return SignedOperation(OperationCode::IBitwiseAnd, is_signed, NO_PRECISE, shift,
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Immediate(0xff));
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return BitfieldExtract(op, static_cast<u32>(byte_height * 8), 8);
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}
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const Node zero = Immediate(0);
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switch (type) {
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case Tegra::Shader::VideoType::Size16_Low:
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return SignedOperation(OperationCode::IBitwiseAnd, is_signed, NO_PRECISE, op,
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Immediate(0xffff));
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return BitfieldExtract(op, 0, 16);
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case Tegra::Shader::VideoType::Size16_High:
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return SignedOperation(OperationCode::ILogicalShiftRight, is_signed, NO_PRECISE, op,
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Immediate(16));
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return BitfieldExtract(op, 16, 16);
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case Tegra::Shader::VideoType::Size32:
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// TODO(Rodrigo): From my hardware tests it becomes a bit "mad" when this type is used
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// (1 * 1 + 0 == 0x5b800000). Until a better explanation is found: abort.
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@ -47,22 +47,10 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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return {false, Immediate(0), Immediate(0)};
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}();
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if (instr.xmad.high_a) {
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op_a = SignedOperation(OperationCode::ILogicalShiftRight, is_signed_a, NO_PRECISE, op_a,
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Immediate(16));
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} else {
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op_a = SignedOperation(OperationCode::IBitwiseAnd, is_signed_a, NO_PRECISE, op_a,
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Immediate(0xffff));
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}
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op_a = BitfieldExtract(op_a, instr.xmad.high_a ? 16 : 0, 16);
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const Node original_b = op_b;
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if (instr.xmad.high_b) {
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op_b = SignedOperation(OperationCode::ILogicalShiftRight, is_signed_b, NO_PRECISE, op_a,
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Immediate(16));
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} else {
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op_b = SignedOperation(OperationCode::IBitwiseAnd, is_signed_b, NO_PRECISE, op_b,
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Immediate(0xffff));
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}
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op_b = BitfieldExtract(op_b, instr.xmad.high_b ? 16 : 0, 16);
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// TODO(Rodrigo): Use an appropiate sign for this operation
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Node product = Operation(OperationCode::IMul, NO_PRECISE, op_a, op_b);
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@ -75,11 +63,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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case Tegra::Shader::XmadMode::None:
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return op_c;
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case Tegra::Shader::XmadMode::CLo:
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return SignedOperation(OperationCode::IBitwiseAnd, is_signed_c, NO_PRECISE, op_c,
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Immediate(0xffff));
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return BitfieldExtract(op_c, 0, 16);
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case Tegra::Shader::XmadMode::CHi:
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return SignedOperation(OperationCode::ILogicalShiftRight, is_signed_c, NO_PRECISE, op_c,
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Immediate(16));
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return BitfieldExtract(op_c, 16, 16);
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case Tegra::Shader::XmadMode::CBcc: {
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const Node shifted_b = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed_b,
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NO_PRECISE, original_b, Immediate(16));
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@ -94,9 +80,9 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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// TODO(Rodrigo): Use an appropiate sign for this operation
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Node sum = Operation(OperationCode::IAdd, product, op_c);
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if (is_merge) {
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const Node a = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, sum, Immediate(0xffff));
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const Node a = BitfieldExtract(sum, 0, 16);
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const Node b =
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Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, original_b, Immediate(0xffff));
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Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, original_b, Immediate(16));
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sum = Operation(OperationCode::IBitwiseOr, NO_PRECISE, a, b);
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}
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@ -348,6 +348,11 @@ void ShaderIR::SetLocalMemory(BasicBlock& bb, Node address, Node value) {
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bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, value, Immediate(offset),
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Immediate(bits));
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}
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/*static*/ OperationCode ShaderIR::SignedToUnsignedCode(OperationCode operation_code,
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bool is_signed) {
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if (is_signed) {
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@ -88,6 +88,7 @@ enum class OperationCode {
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IBitwiseXor, /// (MetaArithmetic, int a, int b) -> int
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IBitwiseNot, /// (MetaArithmetic, int a) -> int
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IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int
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IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int
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IBitCount, /// (MetaArithmetic, int) -> int
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UAdd, /// (MetaArithmetic, uint a, uint b) -> uint
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@ -104,8 +105,9 @@ enum class OperationCode {
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UBitwiseOr, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseXor, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseNot, /// (MetaArithmetic, uint a) -> uint
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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HAdd, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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@ -689,6 +691,9 @@ private:
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const Sampler& GetSampler(const Tegra::Shader::Sampler& sampler,
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Tegra::Shader::TextureType type, bool is_array, bool is_shadow);
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/// Extracts a sequence of bits from a node
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Node BitfieldExtract(Node value, u32 offset, u32 bits);
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void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr, Node texture);
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void WriteTexsInstructionHalfFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
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Node texture);
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