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shader_decode: Implement IADD3
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@ -9,6 +9,7 @@
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namespace VideoCommon::Shader {
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using Tegra::Shader::IAdd3Height;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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@ -42,6 +43,66 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, Operation(OperationCode::IAdd, PRECISE, op_a, op_b));
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break;
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}
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case OpCode::Id::IADD3_C:
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case OpCode::Id::IADD3_R:
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case OpCode::Id::IADD3_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in IADD3 is not implemented");
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Node op_c = GetRegister(instr.gpr39);
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const auto ApplyHeight = [&](IAdd3Height height, Node value) {
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switch (height) {
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case IAdd3Height::None:
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return value;
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case IAdd3Height::LowerHalfWord:
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return Operation(OperationCode::IBitwiseAnd, NO_PRECISE, value, Immediate(0xffff));
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case IAdd3Height::UpperHalfWord:
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return Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, value,
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Immediate(16));
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default:
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UNIMPLEMENTED_MSG("Unhandled IADD3 height: {}", static_cast<u32>(height));
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return Immediate(0);
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}
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};
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if (opcode->get().GetId() == OpCode::Id::IADD3_R) {
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op_a = ApplyHeight(instr.iadd3.height_a, op_a);
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op_b = ApplyHeight(instr.iadd3.height_b, op_b);
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op_c = ApplyHeight(instr.iadd3.height_c, op_c);
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}
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op_a = GetOperandAbsNegInteger(op_a, false, instr.iadd3.neg_a, true);
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op_b = GetOperandAbsNegInteger(op_b, false, instr.iadd3.neg_b, true);
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op_c = GetOperandAbsNegInteger(op_c, false, instr.iadd3.neg_c, true);
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const Node value = [&]() {
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const Node add_ab = Operation(OperationCode::IAdd, NO_PRECISE, op_a, op_b);
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if (opcode->get().GetId() != OpCode::Id::IADD3_R) {
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return Operation(OperationCode::IAdd, NO_PRECISE, add_ab, op_c);
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}
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const Node shifted = [&]() {
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switch (instr.iadd3.mode) {
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case Tegra::Shader::IAdd3Mode::RightShift:
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// TODO(tech4me): According to
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// https://envytools.readthedocs.io/en/latest/hw/graph/maxwell/cuda/int.html?highlight=iadd3
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// The addition between op_a and op_b should be done in uint33, more
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// investigation required
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return Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, add_ab,
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Immediate(16));
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case Tegra::Shader::IAdd3Mode::LeftShift:
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return Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, add_ab,
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Immediate(16));
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default:
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return add_ab;
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}
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}();
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return Operation(OperationCode::IAdd, NO_PRECISE, shifted, op_c);
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}();
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::ISCADD_C:
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case OpCode::Id::ISCADD_R:
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case OpCode::Id::ISCADD_IMM: {
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