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shader_decode: Implement SHR
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@ -16,7 +16,32 @@ u32 ShaderIR::DecodeShift(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED();
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = [&]() {
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if (instr.is_b_imm) {
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return Immediate(instr.alu.GetSignedImm20_20());
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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}
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}();
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switch (opcode->get().GetId()) {
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case OpCode::Id::SHR_C:
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case OpCode::Id::SHR_R:
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case OpCode::Id::SHR_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in SHR is not implemented");
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const Node value = SignedOperation(OperationCode::IArithmeticShiftRight,
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instr.shift.is_signed, PRECISE, op_a, op_b);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled shift instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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