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shader: Implement POPC
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@ -69,6 +69,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/impl.cpp
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frontend/maxwell/translate/impl/impl.h
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frontend/maxwell/translate/impl/integer_add.cpp
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frontend/maxwell/translate/impl/integer_popcount.cpp
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frontend/maxwell/translate/impl/integer_scaled_add.cpp
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frontend/maxwell/translate/impl/integer_set_predicate.cpp
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frontend/maxwell/translate/impl/integer_shift_left.cpp
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@ -228,6 +228,8 @@ Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count)
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Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitBitCount32(EmitContext& ctx, Id value);
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Id EmitBitwiseNot32(EmitContext& ctx, Id a);
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
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@ -106,6 +106,14 @@ Id EmitBitReverse32(EmitContext& ctx, Id value) {
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return ctx.OpBitReverse(ctx.U32[1], value);
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}
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Id EmitBitCount32(EmitContext& ctx, Id value) {
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return ctx.OpBitCount(ctx.U32[1], value);
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}
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Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
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return ctx.OpNot(ctx.U32[1], a);
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}
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1, lhs, rhs);
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}
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@ -808,6 +808,14 @@ U32 IREmitter::BitReverse(const U32& value) {
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return Inst<U32>(Opcode::BitReverse32, value);
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}
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U32 IREmitter::BitCount(const U32& value) {
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return Inst<U32>(Opcode::BitCount32, value);
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}
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U32 IREmitter::BitwiseNot(const U32& a) {
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return Inst<U32>(Opcode::BitwiseNot32, a);
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}
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U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
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return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
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}
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@ -160,6 +160,8 @@ public:
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[[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
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bool is_signed);
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[[nodiscard]] U32 BitReverse(const U32& value);
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[[nodiscard]] U32 BitCount(const U32& value);
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[[nodiscard]] U32 BitwiseNot(const U32& a);
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[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
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[[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);
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@ -232,6 +232,8 @@ OPCODE(BitFieldInsert, U32, U32,
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OPCODE(BitFieldSExtract, U32, U32, U32, U32, )
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OPCODE(BitFieldUExtract, U32, U32, U32, U32, )
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OPCODE(BitReverse32, U32, U32, )
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OPCODE(BitCount32, U32, U32, )
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OPCODE(BitwiseNot32, U32, U32, )
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OPCODE(SLessThan, U1, U32, U32, )
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OPCODE(ULessThan, U1, U32, U32, )
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@ -0,0 +1,36 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void POPC(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<40, 1, u64> tilde;
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} const popc{insn};
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const IR::U32 operand = popc.tilde == 0 ? src : v.ir.BitwiseNot(src);
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const IR::U32 result = v.ir.BitCount(operand);
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v.X(popc.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::POPC_reg(u64 insn) {
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POPC(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::POPC_cbuf(u64 insn) {
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POPC(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::POPC_imm(u64 insn) {
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POPC(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -653,18 +653,6 @@ void TranslatorVisitor::PLONGJMP(u64) {
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ThrowNotImplemented(Opcode::PLONGJMP);
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}
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void TranslatorVisitor::POPC_reg(u64) {
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ThrowNotImplemented(Opcode::POPC_reg);
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}
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void TranslatorVisitor::POPC_cbuf(u64) {
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ThrowNotImplemented(Opcode::POPC_cbuf);
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}
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void TranslatorVisitor::POPC_imm(u64) {
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ThrowNotImplemented(Opcode::POPC_imm);
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}
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void TranslatorVisitor::PRET(u64) {
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ThrowNotImplemented(Opcode::PRET);
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}
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