mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-20 16:33:22 +02:00
shader_ir: std::move Node instance where applicable
These are std::shared_ptr instances underneath the hood, which means copying them isn't as cheap as a regular pointer. Particularly so on weakly-ordered systems. This avoids atomic reference count increments and decrements where they aren't necessary for the core set of operations.
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60926ac16b
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bebbdc2067
@ -46,12 +46,12 @@ void ShaderIR::Decode() {
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coverage_end = shader_info.end;
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if (shader_info.decompilable) {
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disable_flow_stack = true;
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const auto insert_block = ([this](NodeBlock& nodes, u32 label) {
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const auto insert_block = [this](NodeBlock& nodes, u32 label) {
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if (label == exit_branch) {
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return;
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}
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basic_blocks.insert({label, nodes});
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});
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};
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const auto& blocks = shader_info.blocks;
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NodeBlock current_block;
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u32 current_label = exit_branch;
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@ -103,7 +103,7 @@ void ShaderIR::DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end) {
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}
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void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) {
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const auto apply_conditions = ([&](const Condition& cond, Node n) -> Node {
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const auto apply_conditions = [&](const Condition& cond, Node n) -> Node {
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Node result = n;
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if (cond.cc != ConditionCode::T) {
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result = Conditional(GetConditionCode(cond.cc), {result});
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@ -117,7 +117,7 @@ void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) {
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result = Conditional(GetPredicate(pred, is_neg), {result});
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}
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return result;
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});
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};
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if (block.branch.address < 0) {
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if (block.branch.kills) {
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Node n = Operation(OperationCode::Discard);
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@ -12,7 +12,7 @@
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namespace VideoCommon::Shader {
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Node Conditional(Node condition, std::vector<Node> code) {
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return MakeNode<ConditionalNode>(condition, std::move(code));
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return MakeNode<ConditionalNode>(std::move(condition), std::move(code));
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}
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Node Comment(std::string text) {
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@ -61,7 +61,7 @@ Node ShaderIR::GetConstBufferIndirect(u64 index_, u64 offset_, Node node) {
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const auto [entry, is_new] = used_cbufs.try_emplace(index);
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entry->second.MarkAsUsedIndirect();
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const Node final_offset = [&]() {
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Node final_offset = [&] {
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// Attempt to inline constant buffer without a variable offset. This is done to allow
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// tracking LDC calls.
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if (const auto gpr = std::get_if<GprNode>(&*node)) {
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@ -69,9 +69,9 @@ Node ShaderIR::GetConstBufferIndirect(u64 index_, u64 offset_, Node node) {
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return Immediate(offset);
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}
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}
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return Operation(OperationCode::UAdd, NO_PRECISE, node, Immediate(offset));
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return Operation(OperationCode::UAdd, NO_PRECISE, std::move(node), Immediate(offset));
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}();
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return MakeNode<CbufNode>(index, final_offset);
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return MakeNode<CbufNode>(index, std::move(final_offset));
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}
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Node ShaderIR::GetPredicate(u64 pred_, bool negated) {
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@ -89,7 +89,7 @@ Node ShaderIR::GetPredicate(bool immediate) {
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Node ShaderIR::GetInputAttribute(Attribute::Index index, u64 element, Node buffer) {
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used_input_attributes.emplace(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), buffer);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), std::move(buffer));
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}
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Node ShaderIR::GetPhysicalInputAttribute(Tegra::Shader::Register physical_address, Node buffer) {
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@ -122,7 +122,7 @@ Node ShaderIR::GetOutputAttribute(Attribute::Index index, u64 element, Node buff
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}
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used_output_attributes.insert(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), buffer);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), std::move(buffer));
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}
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Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) {
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@ -134,7 +134,7 @@ Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) {
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}
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Node ShaderIR::GetLocalMemory(Node address) {
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return MakeNode<LmemNode>(address);
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return MakeNode<LmemNode>(std::move(address));
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}
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Node ShaderIR::GetTemporary(u32 id) {
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@ -143,10 +143,10 @@ Node ShaderIR::GetTemporary(u32 id) {
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Node ShaderIR::GetOperandAbsNegFloat(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::FAbsolute, NO_PRECISE, value);
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value = Operation(OperationCode::FAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::FNegate, NO_PRECISE, value);
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value = Operation(OperationCode::FNegate, NO_PRECISE, std::move(value));
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}
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return value;
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}
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@ -155,24 +155,26 @@ Node ShaderIR::GetSaturatedFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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const Node positive_zero = Immediate(std::copysignf(0, 1));
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const Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::FClamp, NO_PRECISE, value, positive_zero, positive_one);
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Node positive_zero = Immediate(std::copysignf(0, 1));
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Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::FClamp, NO_PRECISE, std::move(value), std::move(positive_zero),
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std::move(positive_one));
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}
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Node ShaderIR::ConvertIntegerSize(Node value, Tegra::Shader::Register::Size size, bool is_signed) {
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Node ShaderIR::ConvertIntegerSize(Node value, Register::Size size, bool is_signed) {
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switch (size) {
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case Register::Size::Byte:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(24));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(24));
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE,
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std::move(value), Immediate(24));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE,
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std::move(value), Immediate(24));
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return value;
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case Register::Size::Short:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(16));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(16));
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE,
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std::move(value), Immediate(16));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE,
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std::move(value), Immediate(16));
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case Register::Size::Word:
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// Default - do nothing
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return value;
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@ -188,27 +190,29 @@ Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, b
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return value;
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}
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if (absolute) {
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value = Operation(OperationCode::IAbsolute, NO_PRECISE, value);
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value = Operation(OperationCode::IAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::INegate, NO_PRECISE, value);
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value = Operation(OperationCode::INegate, NO_PRECISE, std::move(value));
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}
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return value;
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}
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Node ShaderIR::UnpackHalfImmediate(Instruction instr, bool has_negation) {
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const Node value = Immediate(instr.half_imm.PackImmediates());
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Node value = Immediate(instr.half_imm.PackImmediates());
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if (!has_negation) {
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return value;
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}
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const Node first_negate = GetPredicate(instr.half_imm.first_negate != 0);
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const Node second_negate = GetPredicate(instr.half_imm.second_negate != 0);
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return Operation(OperationCode::HNegate, NO_PRECISE, value, first_negate, second_negate);
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Node first_negate = GetPredicate(instr.half_imm.first_negate != 0);
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Node second_negate = GetPredicate(instr.half_imm.second_negate != 0);
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return Operation(OperationCode::HNegate, NO_PRECISE, std::move(value), std::move(first_negate),
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std::move(second_negate));
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}
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Node ShaderIR::UnpackHalfFloat(Node value, Tegra::Shader::HalfType type) {
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return Operation(OperationCode::HUnpack, type, value);
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return Operation(OperationCode::HUnpack, type, std::move(value));
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}
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Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
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@ -216,11 +220,11 @@ Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
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case Tegra::Shader::HalfMerge::H0_H1:
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return src;
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case Tegra::Shader::HalfMerge::F32:
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return Operation(OperationCode::HMergeF32, src);
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return Operation(OperationCode::HMergeF32, std::move(src));
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case Tegra::Shader::HalfMerge::Mrg_H0:
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return Operation(OperationCode::HMergeH0, dest, src);
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return Operation(OperationCode::HMergeH0, std::move(dest), std::move(src));
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case Tegra::Shader::HalfMerge::Mrg_H1:
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return Operation(OperationCode::HMergeH1, dest, src);
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return Operation(OperationCode::HMergeH1, std::move(dest), std::move(src));
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}
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UNREACHABLE();
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return src;
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@ -228,10 +232,10 @@ Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
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Node ShaderIR::GetOperandAbsNegHalf(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::HAbsolute, NO_PRECISE, value);
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value = Operation(OperationCode::HAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::HNegate, NO_PRECISE, value, GetPredicate(true),
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value = Operation(OperationCode::HNegate, NO_PRECISE, std::move(value), GetPredicate(true),
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GetPredicate(true));
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}
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return value;
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@ -241,9 +245,11 @@ Node ShaderIR::GetSaturatedHalfFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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const Node positive_zero = Immediate(std::copysignf(0, 1));
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const Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::HClamp, NO_PRECISE, value, positive_zero, positive_one);
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Node positive_zero = Immediate(std::copysignf(0, 1));
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Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::HClamp, NO_PRECISE, std::move(value), std::move(positive_zero),
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std::move(positive_one));
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}
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Node ShaderIR::GetPredicateComparisonFloat(PredCondition condition, Node op_a, Node op_b) {
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@ -271,7 +277,6 @@ Node ShaderIR::GetPredicateComparisonFloat(PredCondition condition, Node op_a, N
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condition == PredCondition::LessEqualWithNan ||
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condition == PredCondition::GreaterThanWithNan ||
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condition == PredCondition::GreaterEqualWithNan) {
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predicate = Operation(OperationCode::LogicalOr, predicate,
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Operation(OperationCode::LogicalFIsNan, op_a));
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predicate = Operation(OperationCode::LogicalOr, predicate,
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@ -300,7 +305,8 @@ Node ShaderIR::GetPredicateComparisonInteger(PredCondition condition, bool is_si
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UNIMPLEMENTED_IF_MSG(comparison == PredicateComparisonTable.end(),
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"Unknown predicate comparison operation");
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Node predicate = SignedOperation(comparison->second, is_signed, NO_PRECISE, op_a, op_b);
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Node predicate = SignedOperation(comparison->second, is_signed, NO_PRECISE, std::move(op_a),
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std::move(op_b));
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UNIMPLEMENTED_IF_MSG(condition == PredCondition::LessThanWithNan ||
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condition == PredCondition::NotEqualWithNan ||
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@ -330,9 +336,7 @@ Node ShaderIR::GetPredicateComparisonHalf(Tegra::Shader::PredCondition condition
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UNIMPLEMENTED_IF_MSG(comparison == PredicateComparisonTable.end(),
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"Unknown predicate comparison operation");
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const Node predicate = Operation(comparison->second, NO_PRECISE, op_a, op_b);
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return predicate;
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return Operation(comparison->second, NO_PRECISE, std::move(op_a), std::move(op_b));
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}
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OperationCode ShaderIR::GetPredicateCombiner(PredOperation operation) {
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@ -358,31 +362,32 @@ Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) {
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}
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void ShaderIR::SetRegister(NodeBlock& bb, Register dest, Node src) {
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), std::move(src)));
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}
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void ShaderIR::SetPredicate(NodeBlock& bb, u64 dest, Node src) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetPredicate(dest), src));
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bb.push_back(Operation(OperationCode::LogicalAssign, GetPredicate(dest), std::move(src)));
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}
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void ShaderIR::SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetInternalFlag(flag), value));
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bb.push_back(Operation(OperationCode::LogicalAssign, GetInternalFlag(flag), std::move(value)));
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}
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void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
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bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
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bb.push_back(
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Operation(OperationCode::Assign, GetLocalMemory(std::move(address)), std::move(value)));
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}
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void ShaderIR::SetTemporary(NodeBlock& bb, u32 id, Node value) {
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SetRegister(bb, Register::ZeroIndex + 1 + id, value);
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SetRegister(bb, Register::ZeroIndex + 1 + id, std::move(value));
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}
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void ShaderIR::SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc) {
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if (!sets_cc) {
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return;
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}
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const Node zerop = Operation(OperationCode::LogicalFEqual, value, Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, zerop);
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Node zerop = Operation(OperationCode::LogicalFEqual, std::move(value), Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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@ -390,14 +395,14 @@ void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_
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if (!sets_cc) {
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return;
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}
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const Node zerop = Operation(OperationCode::LogicalIEqual, value, Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, zerop);
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, value, Immediate(offset),
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Immediate(bits));
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return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, std::move(value),
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Immediate(offset), Immediate(bits));
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}
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} // namespace VideoCommon::Shader
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@ -15,18 +15,20 @@ namespace {
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std::pair<Node, s64> FindOperation(const NodeBlock& code, s64 cursor,
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OperationCode operation_code) {
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for (; cursor >= 0; --cursor) {
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const Node node = code.at(cursor);
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Node node = code.at(cursor);
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if (const auto operation = std::get_if<OperationNode>(&*node)) {
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if (operation->GetCode() == operation_code) {
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return {node, cursor};
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return {std::move(node), cursor};
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}
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}
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if (const auto conditional = std::get_if<ConditionalNode>(&*node)) {
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const auto& conditional_code = conditional->GetCode();
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const auto [found, internal_cursor] = FindOperation(
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auto [found, internal_cursor] = FindOperation(
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conditional_code, static_cast<s64>(conditional_code.size() - 1), operation_code);
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if (found) {
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return {found, cursor};
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return {std::move(found), cursor};
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}
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}
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}
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