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shader_ir: Remove RZ and use Register::ZeroIndex instead
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@ -91,12 +91,14 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
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const Node composite =
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Operation(OperationCode::Composite, op_a, op_b, GetRegister(RZ), GetRegister(RZ));
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Operation(OperationCode::Composite, op_a, op_b, GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex));
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MetaComponents meta{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(RZ), GetRegister(RZ)));
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GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex)));
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break;
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}
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default:
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@ -197,7 +199,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture, dest[0],
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dest[1], dest[2], dest[3]));
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@ -255,7 +258,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta_components), texture,
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dest[0], dest[1], dest[2], dest[3]));
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@ -369,7 +373,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const MetaComponents meta_composite{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta_composite, texture,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(RZ), GetRegister(RZ)));
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GetRegister(Register::ZeroIndex), GetRegister(Register::ZeroIndex)));
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break;
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}
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case OpCode::Id::TLDS: {
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@ -438,7 +442,8 @@ void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node
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++meta.count;
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}
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std::generate(dest.begin() + meta.count, dest.end(), [&]() { return GetRegister(RZ); });
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std::generate(dest.begin() + meta.count, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
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dest[3]));
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@ -22,6 +22,7 @@ using Tegra::Shader::Header;
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using Tegra::Shader::IpaInterpMode;
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using Tegra::Shader::IpaMode;
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using Tegra::Shader::IpaSampleMode;
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using Tegra::Shader::Register;
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using namespace VideoCommon::Shader;
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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@ -419,7 +420,7 @@ private:
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} else if (const auto gpr = std::get_if<GprNode>(node)) {
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const u32 index = gpr->GetIndex();
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if (index == RZ) {
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if (index == Register::ZeroIndex) {
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return "0";
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}
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return GetRegister(index);
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@ -728,8 +729,8 @@ private:
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std::string target;
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if (const auto gpr = std::get_if<GprNode>(dest)) {
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if (gpr->GetIndex() == RZ) {
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// Writing to RZ is a no op
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if (gpr->GetIndex() == Register::ZeroIndex) {
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// Writing to Register::ZeroIndex is a no op
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return {};
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}
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target = GetRegister(gpr->GetIndex());
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@ -776,7 +777,7 @@ private:
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constexpr u32 composite_size = 4;
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for (u32 i = 0; i < composite_size; ++i) {
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const auto gpr = std::get<GprNode>(*operation[i + 1]).GetIndex();
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if (gpr == RZ) {
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if (gpr == Register::ZeroIndex) {
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continue;
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}
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code.AddLine(GetRegister(gpr) + " = " + composite +
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@ -41,8 +41,6 @@ using BasicBlock = std::vector<Node>;
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constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
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constexpr u32 RZ = 0xff;
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enum class OperationCode {
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Assign, /// (float& dest, float src) -> void
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AssignComposite, /// (MetaComponents, float4 src, float&[4] dst) -> void
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