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GSP: HLE GXCommandId::SET_DISPLAY_TRANSFER and GXCommandId::SET_TEXTURE_COPY.
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@ -176,10 +176,17 @@ void TriggerCmdReqQueue(Service::Interface* self) {
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case GXCommandId::SET_MEMORY_FILL:
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break;
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// TODO: Check if texture copies are implemented correctly..
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case GXCommandId::SET_DISPLAY_TRANSFER:
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break;
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case GXCommandId::SET_TEXTURE_COPY:
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GPU::Write<u32>(GPU::Registers::DisplayInputBufferAddr, cmd_buff[1] >> 3);
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GPU::Write<u32>(GPU::Registers::DisplayOutputBufferAddr, cmd_buff[2] >> 3);
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GPU::Write<u32>(GPU::Registers::DisplayInputBufferSize, cmd_buff[3]);
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GPU::Write<u32>(GPU::Registers::DisplayOutputBufferSize, cmd_buff[4]);
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GPU::Write<u32>(GPU::Registers::DisplayTransferFlags, cmd_buff[5]);
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// TODO: GPU::Registers::DisplayTriggerTransfer should be ORed with 1 for texture copies?
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GPU::Write<u32>(GPU::Registers::DisplayTriggerTransfer, 1);
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break;
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case GXCommandId::SET_COMMAND_LIST_FIRST:
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@ -22,6 +22,14 @@ struct Registers {
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FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer
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FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer
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DisplayInputBufferAddr = 0x1EF00C00,
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DisplayOutputBufferAddr = 0x1EF00C04,
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DisplayOutputBufferSize = 0x1EF00C08,
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DisplayInputBufferSize = 0x1EF00C0C,
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DisplayTransferFlags = 0x1EF00C10,
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// Unknown??
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DisplayTriggerTransfer = 0x1EF00C18,
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CommandListSize = 0x1EF018E0,
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CommandListAddress = 0x1EF018E8,
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ProcessCommandList = 0x1EF018F0,
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