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Merge pull request #510 from Subv/isetp
GPU: Implemented the ISETP_R and ISETP_C instructions
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commit
f564822e78
@ -238,6 +238,16 @@ union Instruction {
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BitField<56, 1, u64> neg_b;
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} fsetp;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<45, 2, PredOperation> op;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, PredCondition> cond;
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} isetp;
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union {
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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@ -219,6 +219,11 @@ public:
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return active_type == Type::Integer;
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}
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/// Returns the current active type of the register
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Type GetActiveType() const {
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return active_type;
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}
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/// Returns the index of the register
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size_t GetIndex() const {
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return index;
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@ -350,22 +355,28 @@ public:
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shader.AddLine(dest + " = " + src + ';');
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}
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/// Generates code representing a uniform (C buffer) register.
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std::string GetUniform(const Uniform& uniform, const Register& dest_reg) {
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/// Generates code representing a uniform (C buffer) register, interpreted as the input type.
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std::string GetUniform(const Uniform& uniform, GLSLRegister::Type type) {
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declr_const_buffers[uniform.index].MarkAsUsed(static_cast<unsigned>(uniform.index),
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static_cast<unsigned>(uniform.offset), stage);
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std::string value =
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'c' + std::to_string(uniform.index) + '[' + std::to_string(uniform.offset) + ']';
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if (regs[dest_reg].IsFloat()) {
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if (type == GLSLRegister::Type::Float) {
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return value;
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} else if (regs[dest_reg].IsInteger()) {
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} else if (type == GLSLRegister::Type::Integer) {
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return "floatBitsToInt(" + value + ')';
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} else {
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UNREACHABLE();
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}
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}
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/// Generates code representing a uniform (C buffer) register, interpreted as the type of the
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/// destination register.
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std::string GetUniform(const Uniform& uniform, const Register& dest_reg) {
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return GetUniform(uniform, regs[dest_reg].GetActiveType());
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}
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/// Add declarations for registers
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void GenerateDeclarations() {
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for (const auto& reg : regs) {
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@ -1018,7 +1029,7 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsFloat(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Float);
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}
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}
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@ -1049,6 +1060,42 @@ private:
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}
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break;
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}
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case OpCode::Type::IntegerSetPredicate: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, instr.isetp.is_signed);
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std::string op_b{};
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ASSERT_MSG(!instr.is_b_imm, "ISETP_IMM not implemented");
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsInteger(instr.gpr20, 0, instr.isetp.is_signed);
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} else {
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Integer);
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}
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using Tegra::Shader::Pred;
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// We can't use the constant predicate as destination.
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ASSERT(instr.isetp.pred3 != static_cast<u64>(Pred::UnusedIndex));
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std::string second_pred =
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GetPredicateCondition(instr.isetp.pred39, instr.isetp.neg_pred != 0);
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std::string comparator = GetPredicateComparison(instr.isetp.cond);
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std::string combiner = GetPredicateCombiner(instr.isetp.op);
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std::string predicate = '(' + op_a + ") " + comparator + " (" + op_b + ')';
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// Set the primary predicate to the result of Predicate OP SecondPredicate
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SetPredicate(instr.isetp.pred3,
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'(' + predicate + ") " + combiner + " (" + second_pred + ')');
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if (instr.isetp.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
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// Set the secondary predicate to the result of !Predicate OP SecondPredicate,
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// if enabled
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SetPredicate(instr.isetp.pred0,
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"!(" + predicate + ") " + combiner + " (" + second_pred + ')');
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}
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break;
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}
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case OpCode::Type::FloatSet: {
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std::string op_a = instr.fset.neg_a ? "-" : "";
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op_a += regs.GetRegisterAsFloat(instr.gpr8);
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@ -1069,7 +1116,7 @@ private:
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if (instr.is_b_gpr) {
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op_b += regs.GetRegisterAsFloat(instr.gpr20);
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} else {
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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op_b += regs.GetUniform(instr.uniform, GLSLRegister::Type::Float);
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}
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}
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