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3198 Commits

Author SHA1 Message Date
bunnei
19af91434e
Merge pull request #2793 from ReinUsesLisp/bgr565 
renderer_opengl: Implement RGB565 framebuffer format
 2019-09-03 22:36:32 -04:00
bunnei
81fbc5370d
Merge pull request #2812 from ReinUsesLisp/f2i-selector 
shader_ir/conversion: Implement F2I and F2F F16 selector
 2019-09-03 22:35:33 -04:00
bunnei
d4f33b822b
Merge pull request #2811 from ReinUsesLisp/fsetp-fix 
float_set_predicate: Add missing negation bit for the second operand
 2019-09-03 22:34:34 -04:00
bunnei
137d165672
Merge pull request #2826 from ReinUsesLisp/macro-binding 
maxwell_3d: Fix macro binding cursor
 2019-09-03 22:32:42 -04:00
bunnei
50b5bb44a0
Merge pull request #2765 from FernandoS27/dma-fix 
MaxwellDMA: Fixes, corrections and relaxations.
 2019-09-01 13:13:05 -04:00
ReinUsesLisp
52a41f482f maxwell_3d: Fix macro binding cursor 2019-09-01 05:01:11 -03:00
Rodrigo Locatti
4d4f9cc104 video_core: Silent miscellaneous warnings (#2820) 
* texture_cache/surface_params: Remove unused local variable

* rasterizer_interface: Add missing documentation commentary

* maxwell_dma: Remove unused rasterizer reference

* video_core/gpu: Sort member declaration order to silent -Wreorder warning

* fermi_2d: Remove unused MemoryManager reference

* video_core: Silent unused variable warnings

* buffer_cache: Silent -Wreorder warnings

* kepler_memory: Remove unused MemoryManager reference

* gl_texture_cache: Add missing override

* buffer_cache: Add missing include

* shader/decode: Remove unused variables
 2019-08-30 14:08:00 -04:00
ReinUsesLisp
878adee0a3 gl_buffer_cache: Add missing include 
RasterizerInterface was considered an incomplete object by clang.
 2019-08-29 22:02:52 +00:00
bunnei
a67c4e6e02
Merge pull request #2742 from ReinUsesLisp/fix-texture-buffers 
gl_texture_cache: Miscellaneous texture buffer fixes
 2019-08-29 15:59:17 -04:00
bunnei
e424615839
Merge pull request #2783 from FernandoS27/new-buffer-cache 
Implement a New LLE Buffer Cache
 2019-08-29 13:07:01 -04:00
bunnei
f8cc5668f8
Merge pull request #2758 from ReinUsesLisp/packed-tid 
shader/decode: Implement S2R Tic
 2019-08-29 12:58:43 -04:00
ReinUsesLisp
e3534700d7 shader_ir/conversion: Split int and float selector and implement F2F H1 2019-08-28 16:09:33 -03:00
ReinUsesLisp
b13fbc25b8 shader_ir/conversion: Implement F2I F16 Ra.H1 2019-08-27 23:40:40 -03:00
ReinUsesLisp
6207751b00 float_set_predicate: Add missing negation bit for the second operand 2019-08-27 21:57:43 -03:00
ReinUsesLisp
4e35177e23 shader_ir: Implement VOTE 
Implement VOTE using Nvidia's intrinsics. Documentation about these can
be found here
https://developer.nvidia.com/reading-between-threads-shader-intrinsics

Instead of using portable ARB instructions I opted to use Nvidia
intrinsics because these are the closest we have to how Tegra X1
hardware renders.

To stub VOTE on non-Nvidia drivers (including nouveau) this commit
simulates a GPU with a warp size of one, returning what is meaningful
for the instruction being emulated:

* anyThreadNV(value) -> value
* allThreadsNV(value) -> value
* allThreadsEqualNV(value) -> true

ballotARB, also known as "uint64_t(activeThreadsNV())", emits

VOTE.ANY Rd, PT, PT;

on nouveau's compiler. This doesn't match exactly to Nvidia's code

VOTE.ALL Rd, PT, PT;

Which is emulated with activeThreadsNV() by this commit. In theory this
shouldn't really matter since .ANY, .ALL and .EQ affect the predicates
(set to PT on those cases) and not the registers.
 2019-08-21 14:50:38 -03:00
Fernando Sahmkow
83ec2091c1 Buffer Cache: Adress Feedback. 2019-08-21 12:14:27 -04:00
Fernando Sahmkow
6ce2c85047 Buffer_Cache: Implement flushing. 2019-08-21 12:14:26 -04:00
Fernando Sahmkow
de8ff8a1c6 Buffer_Cache: Implement barriers. 2019-08-21 12:14:25 -04:00
Fernando Sahmkow
286f4c446a Buffer_Cache: Optimize and track written areas. 2019-08-21 12:14:25 -04:00
Fernando Sahmkow
5f4b746a1e BufferCache: Rework mapping caching. 2019-08-21 12:14:24 -04:00
Fernando Sahmkow
86d8563314 Buffer_Cache: Fixes and optimizations. 2019-08-21 12:14:23 -04:00
Fernando Sahmkow
862bec001b Video_Core: Implement a new Buffer Cache 2019-08-21 12:14:22 -04:00
bunnei
d654b3d82e
Merge pull request #2769 from FernandoS27/commands-flush 
GPU: Flush commands on every dma pusher step.
 2019-08-21 10:29:56 -04:00
bunnei
dfdd20142e
Merge pull request #2777 from ReinUsesLisp/hsetp2-fe3h-fix 
half_set_predicate: Fix HSETP2_C constant buffer offset
 2019-08-21 10:29:17 -04:00
bunnei
cedc1aab4a
Merge pull request #2753 from FernandoS27/float-convert 
Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
 2019-08-21 10:27:57 -04:00
ReinUsesLisp
80702aa88f renderer_opengl: Implement RGB565 framebuffer format 2019-08-21 02:28:31 -03:00
ReinUsesLisp
9cdf5c6c31 renderer_opengl: Use block linear swizzling for CPU framebuffers 2019-08-21 02:17:14 -03:00
ReinUsesLisp
8ad7268c75 renderer_opengl: Use VideoCore pixel format 2019-08-21 02:16:40 -03:00
ReinUsesLisp
9a76e94b3d gpu: Change optional<reference_wrapper<T>> to T* for FramebufferConfig 2019-08-21 01:55:25 -03:00
bunnei
ca61e298b3
Merge pull request #2778 from ReinUsesLisp/nop 
shader_ir: Implement NOP
 2019-08-18 08:51:34 -04:00
bunnei
87bbefe55f
Merge pull request #2768 from ReinUsesLisp/hsetp2-fix 
decode/half_set_predicate: Fix predicates
 2019-08-18 08:50:54 -04:00
ReinUsesLisp
2ff8044806 shader_ir: Implement NOP 2019-08-04 03:02:55 -03:00
ReinUsesLisp
ec0da3ef64 half_set_predicate: Fix HSETP2_C constant buffer offset 2019-08-04 02:50:55 -03:00
Fernando Sahmkow
e52c895559 GPU: Flush commands on every dma pusher step. 
This commit ensures that the host gpu is constantly fed with commands to
work with, while the guest gpu keeps producing the rest of the commands.
This reduces syncing time between host and guest gpu.
 2019-07-26 16:54:22 -04:00
bunnei
52f54c728d
Merge pull request #2592 from FernandoS27/sync1 
Implement GPU Synchronization Mechanisms & Correct NVFlinger
 2019-07-26 14:26:44 -04:00
ReinUsesLisp
77f1a676a1 decode/half_set_predicate: Fix predicates 2019-07-26 00:12:38 -03:00
Fernando Sahmkow
a452ff983d MaxwellDMA: Fixes, corrections and relaxations. 
This commit fixes offsets on Linear -> Tiled copies, corrects z pos
fortiled->linear copies, corrects bytes_per_pixel calculation in tiled
-> linear copies and relaxes some limitations set by latest dma fixes
refactors.
 2019-07-25 20:41:42 -04:00
bunnei
b0ff3179ef
Merge pull request #2739 from lioncash/cflow 
video_core/control_flow: Minor changes/warning cleanup
 2019-07-25 13:04:56 -04:00
bunnei
4d26550f5f
Merge pull request #2737 from FernandoS27/track-fix 
Shader_Ir: Correct tracking to track from right to left
 2019-07-25 12:41:52 -04:00
bunnei
31e8a61527
Merge pull request #2743 from FernandoS27/surpress-assert 
Downgrade and suppress a series of GPU asserts and debug messages.
 2019-07-25 12:34:36 -04:00
bunnei
9be9600bdc
Merge pull request #2704 from FernandoS27/conditional 
maxwell3d: Implement Conditional Rendering
 2019-07-24 17:07:57 -04:00
ReinUsesLisp
104641db07 shader/decode: Implement S2R Tic 2019-07-22 16:16:10 -03:00
bunnei
f601f25bcc
Merge pull request #2734 from ReinUsesLisp/compute-shaders 
gl_rasterizer: Implement compute shaders
 2019-07-22 11:12:55 -04:00
bunnei
27e10e0442
Merge pull request #2735 from FernandoS27/pipeline-rework 
Rework Dirty Flags in GPU Pipeline, Optimize CBData and Redo Clearing mechanism
 2019-07-21 00:59:52 -04:00
Fernando Sahmkow
11f4e739bd Shader_Ir: Implement F16 Variants of F2F, F2I, I2F. 
This commit takes care of implementing the F16 Variants of the 
conversion instructions and makes sure conversions are done.
 2019-07-20 17:38:25 -04:00
Fernando Sahmkow
7a35178ee2 Maxwell3D: Reorganize and address feedback 2019-07-20 10:18:35 -04:00
Fernando Sahmkow
1158777737 Shader_Ir: Change Debug Asserts for Log Warnings 2019-07-19 22:15:34 -04:00
ReinUsesLisp
45c162444d shader/half_set_predicate: Fix HSETP2 implementation 2019-07-19 22:21:22 -03:00
ReinUsesLisp
6c4985edc9 shader/half_set_predicate: Implement missing HSETP2 variants 2019-07-19 22:20:47 -03:00
Lioncash
c1c89411da video_core/control_flow: Provide operator!= for types with operator== 
Provides operational symmetry for the respective structures.
 2019-07-18 21:03:31 -04:00