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/*-------------------------------------------------------------------------
*
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* s_lock . h
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* Hardware - dependent implementation of spinlocks .
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*
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* NOTE : none of the macros in this file are intended to be called directly .
* Call them through the hardware - independent macros in spin . h .
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*
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* The following hardware - dependent macros must be provided for each
* supported platform :
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*
* void S_INIT_LOCK ( slock_t * lock )
* Initialize a spinlock ( to the unlocked state ) .
*
* void S_LOCK ( slock_t * lock )
* Acquire a spinlock , waiting if necessary .
* Time out and abort ( ) if unable to acquire the lock in a
* " reasonable " amount of time - - - typically ~ 1 minute .
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*
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* void S_UNLOCK ( slock_t * lock )
* Unlock a previously acquired lock .
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*
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* bool S_LOCK_FREE ( slock_t * lock )
* Tests if the lock is free . Returns TRUE if free , FALSE if locked .
* This does * not * change the state of the lock .
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*
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* void SPIN_DELAY ( void )
* Delay operation to occur inside spinlock wait loop .
*
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* Note to implementors : there are default implementations for all these
* macros at the bottom of the file . Check if your platform can use
* these or needs to override them .
*
* Usually , S_LOCK ( ) is implemented in terms of an even lower - level macro
* TAS ( ) :
*
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* int TAS ( slock_t * lock )
* Atomic test - and - set instruction . Attempt to acquire the lock ,
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* but do * not * wait . Returns 0 if successful , nonzero if unable
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* to acquire the lock .
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*
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* TAS ( ) is NOT part of the API , and should never be called directly .
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*
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* CAUTION : on some platforms TAS ( ) may sometimes report failure to acquire
* a lock even when the lock is not locked . For example , on Alpha TAS ( )
* will " fail " if interrupted . Therefore TAS ( ) should always be invoked
* in a retry loop , even if you are certain the lock is free .
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*
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* ANOTHER CAUTION : be sure that TAS ( ) and S_UNLOCK ( ) represent sequence
* points , ie , loads and stores of other values must not be moved across
* a lock or unlock . In most cases it suffices to make the operation be
* done through a " volatile " pointer .
*
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* On most supported platforms , TAS ( ) uses a tas ( ) function written
* in assembly language to execute a hardware atomic - test - and - set
* instruction . Equivalent OS - supplied mutex routines could be used too .
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*
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* If no system - specific TAS ( ) is available ( ie , HAVE_SPINLOCKS is not
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* defined ) , then we fall back on an emulation that uses SysV semaphores
* ( see spin . c ) . This emulation will be MUCH MUCH slower than a proper TAS ( )
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* implementation , because of the cost of a kernel call per lock or unlock .
* An old report is that Postgres spends around 40 % of its time in semop ( 2 )
* when using the SysV semaphore code .
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*
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*
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* Portions Copyright ( c ) 1996 - 2004 , PostgreSQL Global Development Group
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* Portions Copyright ( c ) 1994 , Regents of the University of California
*
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* $ PostgreSQL : pgsql / src / include / storage / s_lock . h , v 1.127 2004 / 08 / 29 04 : 13 : 10 momjian Exp $
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*
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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*/
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# ifndef S_LOCK_H
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# define S_LOCK_H
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# include "storage/pg_sema.h"
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# ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
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# if defined(__GNUC__) || defined(__ICC)
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/*************************************************************************
* All the gcc inlines
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* Gcc consistently defines the CPU as __cpu__ .
* Other compilers use __cpu or __cpu__ so we test for both in those cases .
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*/
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/*----------
* Standard gcc asm format ( assuming " volatile slock_t *lock " ) :
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__asm__ __volatile__ (
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" instruction \n "
" instruction \n "
" instruction \n "
: " =r " ( _res ) , " +m " ( * lock ) // return register, in/out lock value
: " r " ( lock ) // lock pointer, in input register
: " memory " , " cc " ) ; // show clobbered registers here
* The output - operands list ( after first colon ) should always include
* " +m " ( * lock ) , whether or not the asm code actually refers to this
* operand directly . This ensures that gcc believes the value in the
* lock variable is used and set by the asm code . Also , the clobbers
* list ( after third colon ) should always include " memory " ; this prevents
* gcc from thinking it can cache the values of shared - memory fields
* across the asm code . Add " cc " if your asm code changes the condition
* code register , and also list any temp registers the code uses .
* - - - - - - - - - -
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*/
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# if defined(__i386__) || defined(__x86_64__) /* AMD Opteron */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res = 1 ;
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/* Use a non-locking test before asserting the bus lock */
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__asm__ __volatile__ (
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" cmpb $0,%1 \n "
" jne 1f \n "
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" lock \n "
" xchgb %0,%1 \n "
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" 1: \n "
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: " +q " ( _res ) , " +m " ( * lock )
:
: " memory " , " cc " ) ;
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return ( int ) _res ;
}
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# define SPIN_DELAY() spin_delay()
static __inline__ void
spin_delay ( void )
{
__asm__ __volatile__ (
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" rep; nop \n " ) ;
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}
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# endif /* __i386__ || __x86_64__ */
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# if defined(__ia64__) || defined(__ia64) /* __ia64 used by ICC compiler? */
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/* Intel Itanium */
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# define HAS_TEST_AND_SET
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typedef unsigned int slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
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tas ( volatile slock_t * lock )
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{
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long int ret ;
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__asm__ __volatile__ (
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" xchg4 %0=%1,%2 \n "
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: " =r " ( ret ) , " +m " ( * lock )
: " r " ( 1 )
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: " memory " ) ;
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return ( int ) ret ;
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}
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# endif /* __ia64__ || __ia64 */
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# if defined(__arm__) || defined(__arm)
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res = 1 ;
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__asm__ __volatile__ (
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" swpb %0, %0, [%2] \n "
: " +r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " ) ;
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return ( int ) _res ;
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}
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# endif /* __arm__ */
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# if defined(__s390__) || defined(__s390x__)
/* S/390 and S/390x Linux (32- and 64-bit zSeries) */
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# define HAS_TEST_AND_SET
typedef unsigned int slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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int _res = 0 ;
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__asm__ __volatile__ (
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" cs %0,%3,0(%2) \n "
: " +d " ( _res ) , " +m " ( * lock )
: " a " ( lock ) , " d " ( 1 )
: " memory " , " cc " ) ;
return _res ;
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}
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# endif /* __s390__ || __s390x__ */
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# if defined(__sparc__)
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res ;
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__asm__ __volatile__ (
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" ldstub [%2], %0 \n "
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: " =r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " ) ;
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return ( int ) _res ;
}
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# endif /* __sparc__ */
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# if defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
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# define HAS_TEST_AND_SET
# if defined(__powerpc64__)
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typedef unsigned long slock_t ;
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# else
typedef unsigned int slock_t ;
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# endif
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# define TAS(lock) tas(lock)
/*
* NOTE : per the Enhanced PowerPC Architecture manual , v1 .0 dated 7 - May - 2002 ,
* an isync is a sufficient synchronization barrier after a lwarx / stwcx loop .
*/
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static __inline__ int
tas ( volatile slock_t * lock )
{
slock_t _t ;
int _res ;
__asm__ __volatile__ (
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" lwarx %0,0,%3 \n "
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" cmpwi %0,0 \n "
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" bne 1f \n "
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" addi %0,%0,1 \n "
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" stwcx. %0,0,%3 \n "
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" beq 2f \n "
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" 1: li %1,1 \n "
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" b 3f \n "
" 2: \n "
" isync \n "
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" li %1,0 \n "
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" 3: \n "
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: " =&r " ( _t ) , " =r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " , " cc " ) ;
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return _res ;
}
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/* PowerPC S_UNLOCK is almost standard but requires a "sync" instruction */
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# define S_UNLOCK(lock) \
do \
{ \
__asm__ __volatile__ ( " sync \n " ) ; \
* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
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# endif /* powerpc */
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# if defined(__mc68000__) && defined(__linux__)
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
register int rv ;
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__asm__ __volatile__ (
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" clrl %0 \n "
" tas %1 \n "
" sne %0 \n "
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: " =d " ( rv ) , " +m " ( * lock )
:
: " memory " , " cc " ) ;
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return rv ;
}
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# endif /* defined(__mc68000__) && defined(__linux__) */
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# if defined(__vax__)
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/*
* VAXen - - even multiprocessor ones
* ( thanks to Tom Ivar Helbekkmo )
*/
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register int _res ;
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__asm__ __volatile__ (
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" movl $1, %0 \n "
" bbssi $0, (%2), 1f \n "
" clrl %0 \n "
" 1: \n "
: " =&r " ( _res ) , " +m " ( * lock )
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: " r " ( lock )
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: " memory " ) ;
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return _res ;
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}
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# endif /* __vax__ */
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# if defined(__ns32k__)
# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register int _res ;
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__asm__ __volatile__ (
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" sbitb 0, %1 \n "
" sfsd %0 \n "
: " =r " ( _res ) , " +m " ( * lock )
:
: " memory " ) ;
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return _res ;
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}
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# endif /* __ns32k__ */
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# if defined(__alpha) || defined(__alpha__)
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/*
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* Correct multi - processor locking methods are explained in section 5.5 .3
* of the Alpha AXP Architecture Handbook , which at this writing can be
* found at ftp : //ftp.netbsd.org/pub/NetBSD/misc/dec-docs/index.html.
* For gcc we implement the handbook ' s code directly with inline assembler .
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*/
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# define HAS_TEST_AND_SET
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typedef unsigned long slock_t ;
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# define TAS(lock) tas(lock)
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static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res ;
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__asm__ __volatile__ (
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" ldq $0, %1 \n "
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" bne $0, 2f \n "
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" ldq_l %0, %1 \n "
" bne %0, 2f \n "
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" mov 1, $0 \n "
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" stq_c $0, %1 \n "
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" beq $0, 2f \n "
" mb \n "
" br 3f \n "
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" 2: mov 1, %0 \n "
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" 3: \n "
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: " =&r " ( _res ) , " +m " ( * lock )
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:
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: " memory " , " 0 " ) ;
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return ( int ) _res ;
}
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# define S_UNLOCK(lock) \
do \
{ \
__asm__ __volatile__ ( " mb \n " ) ; \
* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
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# endif /* __alpha || __alpha__ */
/* These live in s_lock.c, but only for gcc */
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# if defined(__m68k__)
# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# endif
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# if defined(__mips__) && !defined(__sgi)
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# define HAS_TEST_AND_SET
typedef unsigned char slock_t ;
# endif
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# endif /* __GNUC__ */
/***************************************************************************
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* Platforms that use non - gcc inline assembly :
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*/
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# if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */
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# if defined(USE_UNIVEL_CC)
# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
asm int
tas ( volatile slock_t * s_lock )
{
/* UNIVEL wants %mem in column 1, so we don't pg_indent this file */
% mem s_lock
pushl % ebx
movl s_lock , % ebx
movl $ 255 , % eax
lock
xchgb % al , ( % ebx )
popl % ebx
}
# endif /* defined(USE_UNIVEL_CC) */
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# if defined(__alpha) || defined(__alpha__)
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/*
* The Tru64 compiler doesn ' t support gcc - style inline asm , but it does
* have some builtin functions that accomplish much the same results .
* For simplicity , slock_t is defined as long ( ie , quadword ) on Alpha
* regardless of the compiler in use . LOCK_LONG and UNLOCK_LONG only
* operate on an int ( ie , longword ) , but that ' s OK as long as we define
* S_INIT_LOCK to zero out the whole quadword .
*/
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# define HAS_TEST_AND_SET
typedef unsigned long slock_t ;
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# include <alpha/builtins.h>
# define S_INIT_LOCK(lock) (*(lock) = 0)
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# define TAS(lock) (__LOCK_LONG_RETRY((lock), 1) == 0)
# define S_UNLOCK(lock) __UNLOCK_LONG(lock)
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# endif /* __alpha || __alpha__ */
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# if defined(__hppa) || defined(__hppa__)
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/*
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* HP ' s PA - RISC
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*
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* See src / backend / port / hpux / tas . c . template for details about LDCWX . Because
* LDCWX requires a 16 - byte - aligned address , we declare slock_t as a 16 - byte
* struct . The active word in the struct is whichever has the aligned address ;
* the other three words just sit at - 1.
*
* When using gcc , we can inline the required assembly code .
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*/
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# define HAS_TEST_AND_SET
typedef struct
{
int sema [ 4 ] ;
} slock_t ;
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# define TAS_ACTIVE_WORD(lock) ((volatile int *) (((long) (lock) + 15) & ~15))
# if defined(__GNUC__)
static __inline__ int
tas ( volatile slock_t * lock )
{
volatile int * lockword = TAS_ACTIVE_WORD ( lock ) ;
register int lockval ;
__asm__ __volatile__ (
" ldcwx 0(0,%2),%0 \n "
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: " =r " ( lockval ) , " +m " ( * lockword )
: " r " ( lockword )
: " memory " ) ;
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return ( lockval = = 0 ) ;
}
# endif /* __GNUC__ */
# define S_UNLOCK(lock) (*TAS_ACTIVE_WORD(lock) = -1)
# define S_INIT_LOCK(lock) \
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do { \
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volatile slock_t * lock_ = ( lock ) ; \
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lock_ - > sema [ 0 ] = - 1 ; \
lock_ - > sema [ 1 ] = - 1 ; \
lock_ - > sema [ 2 ] = - 1 ; \
lock_ - > sema [ 3 ] = - 1 ; \
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} while ( 0 )
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# define S_LOCK_FREE(lock) (*TAS_ACTIVE_WORD(lock) != 0)
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# endif /* __hppa || __hppa__ */
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# if defined(__QNX__) && defined(__WATCOMC__)
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/*
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* QNX 4 using WATCOM C
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*/
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# define HAS_TEST_AND_SET
typedef unsigned char slock_t ;
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# define TAS(lock) wc_tas(lock)
extern slock_t wc_tas ( volatile slock_t * lock ) ;
# pragma aux wc_tas =\
" mov al,1 " \
" lock xchg al,[esi] " \
parm [ esi ] \
value [ al ] ;
# endif /* __QNX__ and __WATCOMC__*/
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# if defined(__sgi)
/*
* SGI IRIX 5
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* slock_t is defined as a unsigned long . We use the standard SGI
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* mutex API .
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*
* The following comment is left for historical reasons , but is probably
* not a good idea since the mutex ABI is supported .
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*
* This stuff may be supplemented in the future with Masato Kataoka ' s MIPS - II
* assembly from his NECEWS SVR4 port , but we probably ought to retain this
* for the R3000 chips out there .
*/
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# define HAS_TEST_AND_SET
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typedef unsigned long slock_t ;
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# include "mutex.h"
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# define TAS(lock) (test_and_set(lock,1))
# define S_UNLOCK(lock) (test_then_and(lock,0))
# define S_INIT_LOCK(lock) (test_then_and(lock,0))
# define S_LOCK_FREE(lock) (test_then_add(lock,0) == 0)
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# endif /* __sgi */
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# if defined(sinix)
/*
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* SINIX / Reliant UNIX
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* slock_t is defined as a struct abilock_t , which has a single unsigned long
* member . ( Basically same as SGI )
*/
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# define HAS_TEST_AND_SET
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# include "abi_mutex.h"
typedef abilock_t slock_t ;
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# define TAS(lock) (!acquire_lock(lock))
# define S_UNLOCK(lock) release_lock(lock)
# define S_INIT_LOCK(lock) init_lock(lock)
# define S_LOCK_FREE(lock) (stat_lock(lock) == UNLOCKED)
# endif /* sinix */
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# if defined(_AIX)
/*
* AIX ( POWER )
*/
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# define HAS_TEST_AND_SET
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typedef unsigned int slock_t ;
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# define TAS(lock) _check_lock(lock, 0, 1)
# define S_UNLOCK(lock) _clear_lock(lock, 0)
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# endif /* _AIX */
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# if defined (nextstep)
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# define HAS_TEST_AND_SET
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typedef struct mutex slock_t ;
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# define S_LOCK(lock) mutex_lock(lock)
# define S_UNLOCK(lock) mutex_unlock(lock)
# define S_INIT_LOCK(lock) mutex_init(lock)
/* For Mach, we have to delve inside the entrails of `struct mutex'. Ick! */
# define S_LOCK_FREE(alock) ((alock)->lock == 0)
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# endif /* nextstep */
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/* These are in s_lock.c */
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# if defined(sun3)
# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# endif
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# if defined(__sparc__) || defined(__sparc)
# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
# endif
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# endif /* !defined(HAS_TEST_AND_SET) */
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/* Blow up if we didn't have any way to do spinlocks */
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# ifndef HAS_TEST_AND_SET
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# error PostgreSQL does not have native spinlock support on this platform. To continue the compilation, rerun configure using --disable-spinlocks. However, performance will be poor. Please report this to pgsql-bugs@postgresql.org.
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# endif
# else /* !HAVE_SPINLOCKS */
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/*
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* Fake spinlock implementation using semaphores - - - slow and prone
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* to fall foul of kernel limits on number of semaphores , so don ' t use this
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* unless you must ! The subroutines appear in spin . c .
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*/
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typedef PGSemaphoreData slock_t ;
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extern bool s_lock_free_sema ( volatile slock_t * lock ) ;
extern void s_unlock_sema ( volatile slock_t * lock ) ;
extern void s_init_lock_sema ( volatile slock_t * lock ) ;
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extern int tas_sema ( volatile slock_t * lock ) ;
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# define S_LOCK_FREE(lock) s_lock_free_sema(lock)
# define S_UNLOCK(lock) s_unlock_sema(lock)
# define S_INIT_LOCK(lock) s_init_lock_sema(lock)
# define TAS(lock) tas_sema(lock)
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# endif /* HAVE_SPINLOCKS */
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/*
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* Default Definitions - override these above as needed .
*/
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# if !defined(S_LOCK)
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# define S_LOCK(lock) \
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do { \
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if ( TAS ( lock ) ) \
s_lock ( ( lock ) , __FILE__ , __LINE__ ) ; \
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} while ( 0 )
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# endif /* S_LOCK */
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# if !defined(S_LOCK_FREE)
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# define S_LOCK_FREE(lock) (*(lock) == 0)
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# endif /* S_LOCK_FREE */
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# if !defined(S_UNLOCK)
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# define S_UNLOCK(lock) (*((volatile slock_t *) (lock)) = 0)
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# endif /* S_UNLOCK */
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# if !defined(S_INIT_LOCK)
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# define S_INIT_LOCK(lock) S_UNLOCK(lock)
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# endif /* S_INIT_LOCK */
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# if !defined(SPIN_DELAY)
# define SPIN_DELAY() ((void) 0)
# endif /* SPIN_DELAY */
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# if !defined(TAS)
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extern int tas ( volatile slock_t * lock ) ; /* in port/.../tas.s, or
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* s_lock . c */
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# define TAS(lock) tas(lock)
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# endif /* TAS */
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/*
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* Platform - independent out - of - line support routines
*/
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extern void s_lock ( volatile slock_t * lock , const char * file , int line ) ;
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# endif /* S_LOCK_H */