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/*-------------------------------------------------------------------------
*
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* s_lock . h
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* Hardware - dependent implementation of spinlocks .
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*
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* NOTE : none of the macros in this file are intended to be called directly .
* Call them through the hardware - independent macros in spin . h .
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*
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* The following hardware - dependent macros must be provided for each
* supported platform :
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*
* void S_INIT_LOCK ( slock_t * lock )
* Initialize a spinlock ( to the unlocked state ) .
*
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* int S_LOCK ( slock_t * lock )
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* Acquire a spinlock , waiting if necessary .
* Time out and abort ( ) if unable to acquire the lock in a
* " reasonable " amount of time - - - typically ~ 1 minute .
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* Should return number of " delays " ; see s_lock . c
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*
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* void S_UNLOCK ( slock_t * lock )
* Unlock a previously acquired lock .
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*
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* bool S_LOCK_FREE ( slock_t * lock )
* Tests if the lock is free . Returns TRUE if free , FALSE if locked .
* This does * not * change the state of the lock .
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*
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* void SPIN_DELAY ( void )
* Delay operation to occur inside spinlock wait loop .
*
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* Note to implementors : there are default implementations for all these
* macros at the bottom of the file . Check if your platform can use
* these or needs to override them .
*
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* Usually , S_LOCK ( ) is implemented in terms of even lower - level macros
* TAS ( ) and TAS_SPIN ( ) :
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*
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* int TAS ( slock_t * lock )
* Atomic test - and - set instruction . Attempt to acquire the lock ,
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* but do * not * wait . Returns 0 if successful , nonzero if unable
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* to acquire the lock .
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*
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* int TAS_SPIN ( slock_t * lock )
* Like TAS ( ) , but this version is used when waiting for a lock
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* previously found to be contended . By default , this is the
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* same as TAS ( ) , but on some architectures it ' s better to poll a
* contended lock using an unlocked instruction and retry the
* atomic test - and - set only when it appears free .
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*
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* TAS ( ) and TAS_SPIN ( ) are NOT part of the API , and should never be called
* directly .
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*
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* CAUTION : on some platforms TAS ( ) and / or TAS_SPIN ( ) may sometimes report
* failure to acquire a lock even when the lock is not locked . For example ,
* on Alpha TAS ( ) will " fail " if interrupted . Therefore a retry loop must
* always be used , even if you are certain the lock is free .
*
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* Another caution for users of these macros is that it is the caller ' s
* responsibility to ensure that the compiler doesn ' t re - order accesses
* to shared memory to precede the actual lock acquisition , or follow the
* lock release . Typically we handle this by using volatile - qualified
* pointers to refer to both the spinlock itself and the shared data
* structure being accessed within the spinlocked critical section .
* That fixes it because compilers are not allowed to re - order accesses
* to volatile objects relative to other such accesses .
*
* On platforms with weak memory ordering , the TAS ( ) , TAS_SPIN ( ) , and
* S_UNLOCK ( ) macros must further include hardware - level memory fence
* instructions to prevent similar re - ordering at the hardware level .
* TAS ( ) and TAS_SPIN ( ) must guarantee that loads and stores issued after
* the macro are not executed until the lock has been obtained . Conversely ,
* S_UNLOCK ( ) must guarantee that loads and stores issued before the macro
* have been executed before the lock is released .
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*
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* On most supported platforms , TAS ( ) uses a tas ( ) function written
* in assembly language to execute a hardware atomic - test - and - set
* instruction . Equivalent OS - supplied mutex routines could be used too .
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*
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* If no system - specific TAS ( ) is available ( ie , HAVE_SPINLOCKS is not
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* defined ) , then we fall back on an emulation that uses SysV semaphores
* ( see spin . c ) . This emulation will be MUCH MUCH slower than a proper TAS ( )
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* implementation , because of the cost of a kernel call per lock or unlock .
* An old report is that Postgres spends around 40 % of its time in semop ( 2 )
* when using the SysV semaphore code .
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*
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*
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* Portions Copyright ( c ) 1996 - 2012 , PostgreSQL Global Development Group
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* Portions Copyright ( c ) 1994 , Regents of the University of California
*
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* src / include / storage / s_lock . h
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*
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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*/
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# ifndef S_LOCK_H
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# define S_LOCK_H
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# include "storage/pg_sema.h"
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# ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
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# if defined(__GNUC__) || defined(__INTEL_COMPILER)
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/*************************************************************************
* All the gcc inlines
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* Gcc consistently defines the CPU as __cpu__ .
* Other compilers use __cpu or __cpu__ so we test for both in those cases .
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*/
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/*----------
* Standard gcc asm format ( assuming " volatile slock_t *lock " ) :
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__asm__ __volatile__ (
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" instruction \n "
" instruction \n "
" instruction \n "
: " =r " ( _res ) , " +m " ( * lock ) // return register, in/out lock value
: " r " ( lock ) // lock pointer, in input register
: " memory " , " cc " ) ; // show clobbered registers here
* The output - operands list ( after first colon ) should always include
* " +m " ( * lock ) , whether or not the asm code actually refers to this
* operand directly . This ensures that gcc believes the value in the
* lock variable is used and set by the asm code . Also , the clobbers
* list ( after third colon ) should always include " memory " ; this prevents
* gcc from thinking it can cache the values of shared - memory fields
* across the asm code . Add " cc " if your asm code changes the condition
* code register , and also list any temp registers the code uses .
* - - - - - - - - - -
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*/
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# ifdef __i386__ /* 32-bit i386 */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res = 1 ;
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/*
* Use a non - locking test before asserting the bus lock . Note that the
* extra test appears to be a small loss on some x86 platforms and a small
* win on others ; it ' s by no means clear that we should keep it .
*/
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__asm__ __volatile__ (
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" cmpb $0,%1 \n "
" jne 1f \n "
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" lock \n "
" xchgb %0,%1 \n "
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" 1: \n "
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: " +q " ( _res ) , " +m " ( * lock )
:
: " memory " , " cc " ) ;
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return ( int ) _res ;
}
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# define SPIN_DELAY() spin_delay()
static __inline__ void
spin_delay ( void )
{
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/*
* This sequence is equivalent to the PAUSE instruction ( " rep " is
* ignored by old IA32 processors if the following instruction is
* not a string operation ) ; the IA - 32 Architecture Software
* Developer ' s Manual , Vol . 3 , Section 7.7 .2 describes why using
* PAUSE in the inner loop of a spin lock is necessary for good
* performance :
*
* The PAUSE instruction improves the performance of IA - 32
* processors supporting Hyper - Threading Technology when
* executing spin - wait loops and other routines where one
* thread is accessing a shared lock or semaphore in a tight
* polling loop . When executing a spin - wait loop , the
* processor can suffer a severe performance penalty when
* exiting the loop because it detects a possible memory order
* violation and flushes the core processor ' s pipeline . The
* PAUSE instruction provides a hint to the processor that the
* code sequence is a spin - wait loop . The processor uses this
* hint to avoid the memory order violation and prevent the
* pipeline flush . In addition , the PAUSE instruction
* de - pipelines the spin - wait loop to prevent it from
* consuming execution resources excessively .
*/
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__asm__ __volatile__ (
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" rep; nop \n " ) ;
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}
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# endif /* __i386__ */
# ifdef __x86_64__ /* AMD Opteron, Intel EM64T */
# define HAS_TEST_AND_SET
typedef unsigned char slock_t ;
# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
register slock_t _res = 1 ;
/*
* On Opteron , using a non - locking test before the locking instruction
* is a huge loss . On EM64T , it appears to be a wash or small loss ,
* so we needn ' t bother to try to distinguish the sub - architectures .
*/
__asm__ __volatile__ (
" lock \n "
" xchgb %0,%1 \n "
: " +q " ( _res ) , " +m " ( * lock )
:
: " memory " , " cc " ) ;
return ( int ) _res ;
}
# define SPIN_DELAY() spin_delay()
static __inline__ void
spin_delay ( void )
{
/*
* Adding a PAUSE in the spin delay loop is demonstrably a no - op on
* Opteron , but it may be of some use on EM64T , so we keep it .
*/
__asm__ __volatile__ (
" rep; nop \n " ) ;
}
# endif /* __x86_64__ */
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# if defined(__ia64__) || defined(__ia64)
/*
* Intel Itanium , gcc or Intel ' s compiler .
*
* Itanium has weak memory ordering , but we rely on the compiler to enforce
* strict ordering of accesses to volatile data . In particular , while the
* xchg instruction implicitly acts as a memory barrier with ' acquire '
* semantics , we do not have an explicit memory fence instruction in the
* S_UNLOCK macro . We use a regular assignment to clear the spinlock , and
* trust that the compiler marks the generated store instruction with the
* " .rel " opcode .
*
* Testing shows that assumption to hold on gcc , although I could not find
* any explicit statement on that in the gcc manual . In Intel ' s compiler ,
* the - m [ no - ] serialize - volatile option controls that , and testing shows that
* it is enabled by default .
*/
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# define HAS_TEST_AND_SET
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typedef unsigned int slock_t ;
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# define TAS(lock) tas(lock)
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/* On IA64, it's a win to use a non-locking test before the xchg proper */
# define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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# ifndef __INTEL_COMPILER
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static __inline__ int
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tas ( volatile slock_t * lock )
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{
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long int ret ;
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__asm__ __volatile__ (
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" xchg4 %0=%1,%2 \n "
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: " =r " ( ret ) , " +m " ( * lock )
: " r " ( 1 )
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: " memory " ) ;
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return ( int ) ret ;
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}
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# else /* __INTEL_COMPILER */
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static __inline__ int
tas ( volatile slock_t * lock )
{
int ret ;
ret = _InterlockedExchange ( lock , 1 ) ; /* this is a xchg asm macro */
return ret ;
}
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# endif /* __INTEL_COMPILER */
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# endif /* __ia64__ || __ia64 */
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/*
* On ARM , we use __sync_lock_test_and_set ( int * , int ) if available , and if
* not fall back on the SWPB instruction . SWPB does not work on ARMv6 or
* later , so the compiler builtin is preferred if available . Note also that
* the int - width variant of the builtin works on more chips than other widths .
*/
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# if defined(__arm__) || defined(__arm)
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# define HAS_TEST_AND_SET
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# define TAS(lock) tas(lock)
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# ifdef HAVE_GCC_INT_ATOMICS
typedef int slock_t ;
static __inline__ int
tas ( volatile slock_t * lock )
{
return __sync_lock_test_and_set ( lock , 1 ) ;
}
# define S_UNLOCK(lock) __sync_lock_release(lock)
# else /* !HAVE_GCC_INT_ATOMICS */
typedef unsigned char slock_t ;
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static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res = 1 ;
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__asm__ __volatile__ (
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" swpb %0, %0, [%2] \n "
: " +r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " ) ;
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return ( int ) _res ;
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}
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# endif /* HAVE_GCC_INT_ATOMICS */
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# endif /* __arm__ */
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/* S/390 and S/390x Linux (32- and 64-bit zSeries) */
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# if defined(__s390__) || defined(__s390x__)
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# define HAS_TEST_AND_SET
typedef unsigned int slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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int _res = 0 ;
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__asm__ __volatile__ (
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" cs %0,%3,0(%2) \n "
: " +d " ( _res ) , " +m " ( * lock )
: " a " ( lock ) , " d " ( 1 )
: " memory " , " cc " ) ;
return _res ;
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}
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# endif /* __s390__ || __s390x__ */
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# if defined(__sparc__) /* Sparc */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res ;
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/*
* See comment in / pg / backend / port / tas / solaris_sparc . s for why this
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* uses " ldstub " , and that file uses " cas " . gcc currently generates
* sparcv7 - targeted binaries , so " cas " use isn ' t possible .
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*/
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__asm__ __volatile__ (
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" ldstub [%2], %0 \n "
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: " =r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " ) ;
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return ( int ) _res ;
}
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# endif /* __sparc__ */
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/* PowerPC */
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# if defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
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# define HAS_TEST_AND_SET
typedef unsigned int slock_t ;
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# define TAS(lock) tas(lock)
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/* On PPC, it's a win to use a non-locking test before the lwarx */
# define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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/*
* NOTE : per the Enhanced PowerPC Architecture manual , v1 .0 dated 7 - May - 2002 ,
* an isync is a sufficient synchronization barrier after a lwarx / stwcx loop .
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* On newer machines , we can use lwsync instead for better performance .
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*/
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static __inline__ int
tas ( volatile slock_t * lock )
{
slock_t _t ;
int _res ;
__asm__ __volatile__ (
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# ifdef USE_PPC_LWARX_MUTEX_HINT
" lwarx %0,0,%3,1 \n "
# else
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" lwarx %0,0,%3 \n "
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# endif
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" cmpwi %0,0 \n "
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" bne 1f \n "
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" addi %0,%0,1 \n "
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" stwcx. %0,0,%3 \n "
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" beq 2f \n "
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" 1: li %1,1 \n "
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" b 3f \n "
" 2: \n "
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# ifdef USE_PPC_LWSYNC
" lwsync \n "
# else
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" isync \n "
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# endif
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" li %1,0 \n "
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" 3: \n "
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: " =&r " ( _t ) , " =r " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " , " cc " ) ;
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return _res ;
}
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/*
* PowerPC S_UNLOCK is almost standard but requires a " sync " instruction .
* On newer machines , we can use lwsync instead for better performance .
*/
# ifdef USE_PPC_LWSYNC
# define S_UNLOCK(lock) \
do \
{ \
__asm__ __volatile__ ( " lwsync \n " ) ; \
* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
# else
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# define S_UNLOCK(lock) \
do \
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{ \
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__asm__ __volatile__ ( " sync \n " ) ; \
* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
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# endif /* USE_PPC_LWSYNC */
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# endif /* powerpc */
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/* Linux Motorola 68k */
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# if (defined(__mc68000__) || defined(__m68k__)) && defined(__linux__)
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
register int rv ;
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__asm__ __volatile__ (
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" clrl %0 \n "
" tas %1 \n "
" sne %0 \n "
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: " =d " ( rv ) , " +m " ( * lock )
:
: " memory " , " cc " ) ;
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return rv ;
}
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# endif /* (__mc68000__ || __m68k__) && __linux__ */
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/*
* VAXen - - even multiprocessor ones
* ( thanks to Tom Ivar Helbekkmo )
*/
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# if defined(__vax__)
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register int _res ;
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__asm__ __volatile__ (
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" movl $1, %0 \n "
" bbssi $0, (%2), 1f \n "
" clrl %0 \n "
" 1: \n "
: " =&r " ( _res ) , " +m " ( * lock )
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: " r " ( lock )
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: " memory " ) ;
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return _res ;
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}
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2003-12-23 04:31:30 +01:00
# endif /* __vax__ */
1998-06-16 09:18:16 +02:00
2005-12-17 21:15:43 +01:00
# if defined(__ns32k__) /* National Semiconductor 32K */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
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register int _res ;
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__asm__ __volatile__ (
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" sbitb 0, %1 \n "
" sfsd %0 \n "
: " =r " ( _res ) , " +m " ( * lock )
:
: " memory " ) ;
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return _res ;
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}
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# endif /* __ns32k__ */
1998-02-13 06:10:06 +01:00
1999-11-23 20:47:14 +01:00
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# if defined(__alpha) || defined(__alpha__) /* Alpha */
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/*
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* Correct multi - processor locking methods are explained in section 5.5 .3
* of the Alpha AXP Architecture Handbook , which at this writing can be
* found at ftp : //ftp.netbsd.org/pub/NetBSD/misc/dec-docs/index.html.
* For gcc we implement the handbook ' s code directly with inline assembler .
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*/
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# define HAS_TEST_AND_SET
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2003-12-23 19:13:17 +01:00
typedef unsigned long slock_t ;
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# define TAS(lock) tas(lock)
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static __inline__ int
tas ( volatile slock_t * lock )
{
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register slock_t _res ;
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__asm__ __volatile__ (
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" ldq $0, %1 \n "
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" bne $0, 2f \n "
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" ldq_l %0, %1 \n "
" bne %0, 2f \n "
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" mov 1, $0 \n "
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" stq_c $0, %1 \n "
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" beq $0, 2f \n "
" mb \n "
" br 3f \n "
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" 2: mov 1, %0 \n "
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" 3: \n "
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: " =&r " ( _res ) , " +m " ( * lock )
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:
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: " memory " , " 0 " ) ;
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return ( int ) _res ;
}
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2004-06-20 01:02:32 +02:00
# define S_UNLOCK(lock) \
do \
{ \
__asm__ __volatile__ ( " mb \n " ) ; \
* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
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# endif /* __alpha || __alpha__ */
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# if defined(__mips__) && !defined(__sgi) /* non-SGI MIPS */
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/* Note: on SGI we use the OS' mutex ABI, see below */
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/* Note: R10000 processors require a separate SYNC */
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# define HAS_TEST_AND_SET
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2005-08-25 19:17:10 +02:00
typedef unsigned int slock_t ;
2003-12-23 19:13:17 +01:00
2005-08-25 19:17:10 +02:00
# define TAS(lock) tas(lock)
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2005-08-25 19:17:10 +02:00
static __inline__ int
tas ( volatile slock_t * lock )
{
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register volatile slock_t * _l = lock ;
register int _res ;
register int _tmp ;
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__asm__ __volatile__ (
" .set push \n "
" .set mips2 \n "
" .set noreorder \n "
" .set nomacro \n "
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" ll %0, %2 \n "
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" or %1, %0, 1 \n "
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" sc %1, %2 \n "
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" xori %1, 1 \n "
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" or %0, %0, %1 \n "
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" sync \n "
" .set pop "
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: " =&r " ( _res ) , " =&r " ( _tmp ) , " +R " ( * _l )
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:
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: " memory " ) ;
return _res ;
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}
2003-12-23 04:31:30 +01:00
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/* MIPS S_UNLOCK is almost standard but requires a "sync" instruction */
# define S_UNLOCK(lock) \
do \
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{ \
__asm__ __volatile__ ( \
" .set push \n " \
" .set mips2 \n " \
" .set noreorder \n " \
" .set nomacro \n " \
" sync \n " \
" .set pop " ) ; \
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* ( ( volatile slock_t * ) ( lock ) ) = 0 ; \
} while ( 0 )
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# endif /* __mips__ && !__sgi */
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# if defined(__m32r__) && defined(HAVE_SYS_TAS_H) /* Renesas' M32R */
# define HAS_TEST_AND_SET
# include <sys/tas.h>
typedef int slock_t ;
# define TAS(lock) tas(lock)
# endif /* __m32r__ */
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# if defined(__sh__) /* Renesas' SuperH */
# define HAS_TEST_AND_SET
typedef unsigned char slock_t ;
# define TAS(lock) tas(lock)
static __inline__ int
tas ( volatile slock_t * lock )
{
register int _res ;
/*
* This asm is coded as if % 0 could be any register , but actually SuperH
* restricts the target of xor - immediate to be R0 . That ' s handled by
* the " z " constraint on _res .
*/
__asm__ __volatile__ (
" tas.b @%2 \n "
" movt %0 \n "
" xor #1,%0 \n "
: " =z " ( _res ) , " +m " ( * lock )
: " r " ( lock )
: " memory " , " t " ) ;
return _res ;
}
# endif /* __sh__ */
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/* These live in s_lock.c, but only for gcc */
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# if defined(__m68k__) && !defined(__linux__) /* non-Linux Motorola 68k */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# endif
2003-12-23 19:13:17 +01:00
2008-10-29 17:06:47 +01:00
# endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
2003-12-23 04:31:30 +01:00
2005-12-17 21:39:16 +01:00
/*
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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* Platforms that use non - gcc inline assembly :
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* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2003-12-23 04:31:30 +01:00
*/
2003-12-23 04:52:10 +01:00
# if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */
2003-12-23 04:31:30 +01:00
2003-12-23 19:13:17 +01:00
2005-12-17 21:39:16 +01:00
# if defined(USE_UNIVEL_CC) /* Unixware compiler */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# define TAS(lock) tas(lock)
asm int
tas ( volatile slock_t * s_lock )
{
/* UNIVEL wants %mem in column 1, so we don't pg_indent this file */
% mem s_lock
pushl % ebx
movl s_lock , % ebx
movl $ 255 , % eax
lock
xchgb % al , ( % ebx )
popl % ebx
}
# endif /* defined(USE_UNIVEL_CC) */
2000-12-30 03:34:56 +01:00
2005-12-17 21:39:16 +01:00
# if defined(__alpha) || defined(__alpha__) /* Tru64 Unix Alpha compiler */
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/*
* The Tru64 compiler doesn ' t support gcc - style inline asm , but it does
* have some builtin functions that accomplish much the same results .
* For simplicity , slock_t is defined as long ( ie , quadword ) on Alpha
* regardless of the compiler in use . LOCK_LONG and UNLOCK_LONG only
* operate on an int ( ie , longword ) , but that ' s OK as long as we define
* S_INIT_LOCK to zero out the whole quadword .
*/
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# define HAS_TEST_AND_SET
typedef unsigned long slock_t ;
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# include <alpha/builtins.h>
# define S_INIT_LOCK(lock) (*(lock) = 0)
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# define TAS(lock) (__LOCK_LONG_RETRY((lock), 1) == 0)
# define S_UNLOCK(lock) __UNLOCK_LONG(lock)
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2003-12-23 00:36:38 +01:00
# endif /* __alpha || __alpha__ */
1999-11-23 20:47:14 +01:00
2005-12-17 21:39:16 +01:00
# if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */
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/*
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* HP ' s PA - RISC
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*
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* See src / backend / port / hpux / tas . c . template for details about LDCWX . Because
* LDCWX requires a 16 - byte - aligned address , we declare slock_t as a 16 - byte
* struct . The active word in the struct is whichever has the aligned address ;
* the other three words just sit at - 1.
*
* When using gcc , we can inline the required assembly code .
1998-07-18 16:51:10 +02:00
*/
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# define HAS_TEST_AND_SET
typedef struct
{
int sema [ 4 ] ;
} slock_t ;
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2009-12-31 20:41:37 +01:00
# define TAS_ACTIVE_WORD(lock) ((volatile int *) (((uintptr_t) (lock) + 15) & ~15))
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# if defined(__GNUC__)
static __inline__ int
tas ( volatile slock_t * lock )
{
volatile int * lockword = TAS_ACTIVE_WORD ( lock ) ;
register int lockval ;
__asm__ __volatile__ (
" ldcwx 0(0,%2),%0 \n "
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: " =r " ( lockval ) , " +m " ( * lockword )
: " r " ( lockword )
: " memory " ) ;
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return ( lockval = = 0 ) ;
}
# endif /* __GNUC__ */
# define S_UNLOCK(lock) (*TAS_ACTIVE_WORD(lock) = -1)
# define S_INIT_LOCK(lock) \
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do { \
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volatile slock_t * lock_ = ( lock ) ; \
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lock_ - > sema [ 0 ] = - 1 ; \
lock_ - > sema [ 1 ] = - 1 ; \
lock_ - > sema [ 2 ] = - 1 ; \
lock_ - > sema [ 3 ] = - 1 ; \
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} while ( 0 )
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2003-12-23 23:15:07 +01:00
# define S_LOCK_FREE(lock) (*TAS_ACTIVE_WORD(lock) != 0)
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2004-01-03 06:47:44 +01:00
# endif /* __hppa || __hppa__ */
1998-02-13 06:10:06 +01:00
2003-12-23 04:31:30 +01:00
2004-09-02 19:10:58 +02:00
# if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
2012-03-16 09:14:45 +01:00
/*
* HP - UX on Itanium , non - gcc compiler
*
* We assume that the compiler enforces strict ordering of loads / stores on
* volatile data ( see comments on the gcc - version earlier in this file ) .
* Note that this assumption does * not * hold if you use the
* + Ovolatile = __unordered option on the HP - UX compiler , so don ' t do that .
*
* See also Implementing Spinlocks on the Intel Itanium Architecture and
* PA - RISC , by Tor Ekqvist and David Graves , for more information . As of
* this writing , version 1.0 of the manual is available at :
* http : //h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
*/
2004-09-02 19:10:58 +02:00
# define HAS_TEST_AND_SET
typedef unsigned int slock_t ;
# include <ia64/sys/inline.h>
# define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE)
2011-08-29 19:18:44 +02:00
/* On IA64, it's a win to use a non-locking test before the xchg proper */
# define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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# endif /* HPUX on IA64, non gcc */
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# if defined(__sgi) /* SGI compiler */
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/*
* SGI IRIX 5
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* slock_t is defined as a unsigned long . We use the standard SGI
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* mutex API .
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*
* The following comment is left for historical reasons , but is probably
* not a good idea since the mutex ABI is supported .
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*
* This stuff may be supplemented in the future with Masato Kataoka ' s MIPS - II
* assembly from his NECEWS SVR4 port , but we probably ought to retain this
* for the R3000 chips out there .
*/
2003-12-23 04:31:30 +01:00
# define HAS_TEST_AND_SET
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typedef unsigned long slock_t ;
1999-07-16 01:04:24 +02:00
# include "mutex.h"
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# define TAS(lock) (test_and_set(lock,1))
# define S_UNLOCK(lock) (test_then_and(lock,0))
# define S_INIT_LOCK(lock) (test_then_and(lock,0))
# define S_LOCK_FREE(lock) (test_then_add(lock,0) == 0)
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# endif /* __sgi */
1998-07-18 16:58:58 +02:00
2003-12-23 04:31:30 +01:00
2005-12-17 22:08:24 +01:00
# if defined(sinix) /* Sinix */
1998-09-21 04:25:29 +02:00
/*
2001-01-19 03:58:59 +01:00
* SINIX / Reliant UNIX
1998-09-21 04:25:29 +02:00
* slock_t is defined as a struct abilock_t , which has a single unsigned long
* member . ( Basically same as SGI )
*/
2003-12-23 04:31:30 +01:00
# define HAS_TEST_AND_SET
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# include "abi_mutex.h"
typedef abilock_t slock_t ;
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# define TAS(lock) (!acquire_lock(lock))
# define S_UNLOCK(lock) release_lock(lock)
# define S_INIT_LOCK(lock) init_lock(lock)
# define S_LOCK_FREE(lock) (stat_lock(lock) == UNLOCKED)
# endif /* sinix */
2001-01-19 03:58:59 +01:00
1998-07-18 16:58:58 +02:00
2005-12-17 21:39:16 +01:00
# if defined(_AIX) /* AIX */
1998-07-18 16:58:58 +02:00
/*
* AIX ( POWER )
*/
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# define HAS_TEST_AND_SET
2003-12-23 19:13:17 +01:00
2007-07-16 04:03:14 +02:00
# include <sys/atomic_op.h>
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typedef int slock_t ;
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2007-07-16 06:57:57 +02:00
# define TAS(lock) _check_lock((slock_t *) (lock), 0, 1)
# define S_UNLOCK(lock) _clear_lock((slock_t *) (lock), 0)
1998-09-01 06:40:42 +02:00
# endif /* _AIX */
1998-07-18 16:58:58 +02:00
2003-12-23 04:31:30 +01:00
/* These are in s_lock.c */
1998-07-18 16:58:58 +02:00
2003-12-23 19:13:17 +01:00
2005-12-17 21:39:16 +01:00
# if defined(sun3) /* Sun3 */
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# define HAS_TEST_AND_SET
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typedef unsigned char slock_t ;
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# endif
2003-12-23 19:13:17 +01:00
2008-10-29 17:06:47 +01:00
# if defined(__SUNPRO_C) && (defined(__i386) || defined(__x86_64__) || defined(__sparc__) || defined(__sparc))
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# define HAS_TEST_AND_SET
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2006-05-19 15:10:11 +02:00
# if defined(__i386) || defined(__x86_64__) || defined(__sparcv9) || defined(__sparcv8plus)
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typedef unsigned int slock_t ;
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# else
typedef unsigned char slock_t ;
# endif
2004-09-24 02:21:32 +02:00
2006-04-28 05:43:19 +02:00
extern slock_t pg_atomic_cas ( volatile slock_t * lock , slock_t with ,
2006-04-28 00:28:42 +02:00
slock_t cmp ) ;
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2006-04-28 00:28:42 +02:00
# define TAS(a) (pg_atomic_cas((a), 1, 0) != 0)
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# endif
2006-06-08 00:24:46 +02:00
# ifdef WIN32_ONLY_COMPILER
typedef LONG slock_t ;
# define HAS_TEST_AND_SET
# define TAS(lock) (InterlockedCompareExchange(lock, 1, 0))
# define SPIN_DELAY() spin_delay()
2010-01-04 18:10:24 +01:00
/* If using Visual C++ on Win64, inline assembly is unavailable.
2010-01-05 12:06:28 +01:00
* Use a _mm_pause instrinsic instead of rep nop .
2010-01-04 18:10:24 +01:00
*/
# if defined(_WIN64)
static __forceinline void
spin_delay ( void )
{
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_mm_pause ( ) ;
2010-01-04 18:10:24 +01:00
}
# else
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static __forceinline void
spin_delay ( void )
{
/* See comment for gcc code. Same code, MASM syntax */
__asm rep nop ;
}
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# endif
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# endif
2010-11-23 21:27:50 +01:00
2003-12-23 19:13:17 +01:00
# endif /* !defined(HAS_TEST_AND_SET) */
2003-09-12 18:10:27 +02:00
2003-12-23 04:31:30 +01:00
2003-12-23 19:13:17 +01:00
/* Blow up if we didn't have any way to do spinlocks */
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# ifndef HAS_TEST_AND_SET
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# error PostgreSQL does not have native spinlock support on this platform. To continue the compilation, rerun configure using --disable-spinlocks. However, performance will be poor. Please report this to pgsql-bugs@postgresql.org.
2003-12-23 19:13:17 +01:00
# endif
# else /* !HAVE_SPINLOCKS */
2003-12-23 04:31:30 +01:00
2000-12-29 22:31:21 +01:00
/*
2002-05-05 02:03:29 +02:00
* Fake spinlock implementation using semaphores - - - slow and prone
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* to fall foul of kernel limits on number of semaphores , so don ' t use this
2001-09-29 06:02:27 +02:00
* unless you must ! The subroutines appear in spin . c .
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*/
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typedef PGSemaphoreData slock_t ;
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extern bool s_lock_free_sema ( volatile slock_t * lock ) ;
extern void s_unlock_sema ( volatile slock_t * lock ) ;
extern void s_init_lock_sema ( volatile slock_t * lock ) ;
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extern int tas_sema ( volatile slock_t * lock ) ;
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2001-01-19 03:58:59 +01:00
# define S_LOCK_FREE(lock) s_lock_free_sema(lock)
# define S_UNLOCK(lock) s_unlock_sema(lock)
# define S_INIT_LOCK(lock) s_init_lock_sema(lock)
# define TAS(lock) tas_sema(lock)
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2003-12-23 19:13:17 +01:00
# endif /* HAVE_SPINLOCKS */
2000-12-29 22:31:21 +01:00
1998-07-18 16:58:58 +02:00
2001-09-29 06:02:27 +02:00
/*
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* Default Definitions - override these above as needed .
*/
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# if !defined(S_LOCK)
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# define S_LOCK(lock) \
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( TAS ( lock ) ? s_lock ( ( lock ) , __FILE__ , __LINE__ ) : 0 )
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# endif /* S_LOCK */
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# if !defined(S_LOCK_FREE)
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# define S_LOCK_FREE(lock) (*(lock) == 0)
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# endif /* S_LOCK_FREE */
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# if !defined(S_UNLOCK)
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# define S_UNLOCK(lock) (*((volatile slock_t *) (lock)) = 0)
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# endif /* S_UNLOCK */
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# if !defined(S_INIT_LOCK)
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# define S_INIT_LOCK(lock) S_UNLOCK(lock)
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# endif /* S_INIT_LOCK */
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# if !defined(SPIN_DELAY)
# define SPIN_DELAY() ((void) 0)
# endif /* SPIN_DELAY */
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# if !defined(TAS)
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extern int tas ( volatile slock_t * lock ) ; /* in port/.../tas.s, or
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* s_lock . c */
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# define TAS(lock) tas(lock)
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# endif /* TAS */
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# if !defined(TAS_SPIN)
# define TAS_SPIN(lock) TAS(lock)
# endif /* TAS_SPIN */
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/*
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* Platform - independent out - of - line support routines
*/
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extern int s_lock ( volatile slock_t * lock , const char * file , int line ) ;
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/* Support for dynamic adjustment of spins_per_delay */
# define DEFAULT_SPINS_PER_DELAY 100
extern void set_spins_per_delay ( int shared_spins_per_delay ) ;
extern int update_spins_per_delay ( int shared_spins_per_delay ) ;
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# endif /* S_LOCK_H */